LM3S2776 Datasheet, PDF (534/785 Pages) Texas Instruments – Stellaris® LM3S2776 Microcontroller

Synchronous Serial Interface (SSI)
(GPIOAFSEL) register (page 368) should be set to choose the SSI function. For more information
on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 348.
Table 14-1. SSI Signals (64LQFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SSI0Clk
19
I/O
TTL
SSI module 0 clock.
SSI0Fss
20
I/O
TTL
SSI module 0 frame.
SSI0Rx
21
I
TTL
SSI module 0 receive.
SSI0Tx
22
O
TTL
SSI module 0 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
14.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes. The SSI also supports the DMA interface. The transmit and receive FIFOs can
be programmed as destination/source addresses in the DMA module. DMA operation is enabled
by setting the appropriate bit(s) in the SSIDMACTL register (see page 559).
14.3.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 553). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 546).
The frequency of the output clock SSIClk is defined by:
SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
14.3.2
Note: For master mode, the system clock must be at least two times faster than the SSIClk. For
slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 731 to view SSI timing parameters.
FIFO Operation
14.3.2.1
Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 550), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to
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November 17, 2011
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