LM3S2776 Datasheet, PDF (174/785 Pages) Texas Instruments – Stellaris® LM3S2776 Microcontroller

System Control
5.2.2.6
5.2.3
5.2.3.1
5.2.3.2
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 21-7 on page 728.
Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The watchdog reset timing is shown in Figure 21-8 on page 728.
Non-Maskable Interrupt
The controller has two sources of non-maskable interrupt (NMI):
■ The assertion of the NMI signal.
■ A main oscillator verification error.
If both sources of NMI are enabled, software must check that the main oscillator verification is the
cause of the interrupt in order to distinguish between the two sources.
NMI Pin
The alternate function to GPIO port pin B7 is an NMI signal. The alternate function must be enabled
in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs
(GPIOs)” on page 348. Note that enabling the NMI alternate function requires the use of the GPIO
lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality. The
active sense of the NMI signal is High; asserting the enabled NMI signal above V_IH initiates the NMI
interrupt sequence.
Main Oscillator Verification Failure
The main oscillator verification circuit may generate a reset event, at which time a Power-on Reset
is generated and control is transferred to the NMI handler. The NMI handler is used to address the
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November 17, 2011
Texas Instruments-Production Data