OMAP4460 Datasheet, PDF (69/444 Pages) Texas Instruments – Multimedia Device

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OMAP4460
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SWPS046A – JANUARY 2012
complete specification on the electrical characteristics.
No specific capacitive load is needed in DSI high-speed mode.
The PCB interconnect must be 50-Ω transmission line on DSI dsi_dx[2;0] and DSI dsi_dy[2;0]. DSI dsi_dx[2;0] and DSI dsi_dy[2;0] lines
must be well matched. See Chapter 7 of the MIPI D-PHY standard v1.0 for complete specification of the interconnect.
(12) The buffer strength of this IO cell is programmable (2.5, 5, 7.5, or 10 mA); the default value is described in the table above.
(13) IO drive strength for D+ (usba0_otg_dp) and D– (usba0_otg_dm): minimum 18.3 mA, maximum 89 mA (for a power supply
vdda_usba0otg_3p3v = 3.6 V).
Ball characteristics are compliant with USB2.0.
(14) PU = minimum 900 Ω, maximum 3.090 kΩ and PD = minimum 14.25 kΩ, maximum 24.8 kΩ. Note that:
– PU is typically connected for D+ (usba0_otg_dp) in Full Speed mode and for D– (usba0_otg_dm) in Low Speed mode.
– PD is typically connected for D+ (usba0_otg_dp) and D– (usba0_otg_dm) whatever the modes. PD is connected to both D+ and D–
only if OMAP4 is used as HOST.
Ball characteristics are compliant with USB2.0.
(15) For H2 / H3 / H4 / D2 / E3 / E4 / E2 / E1 / F4 / F3 / F1 / G2 / G4 / G3 / J2 balls, the hysteresis value is equal to 100 mV minimum for
1.8 V (vdds_mmc1 or vdds_usim following the interface used), or 50 mV minimum for 3.0 V (vdds_mmc1 or vdds_usim following the
interface used).
(16) The buffer drive strength is configurable by software programming:
– Mode 2: DS0 = 0, impedance = 50 Ω (buffer drive strength = 4 mA, I_OL = I_OH = 4 mA)
– Mode 1: DS0 = 1, impedance = 25 Ω (buffer drive strength = 8 mA, I_OL = I_OH = 8 mA)
In the BUFFER STRENGTH (mA) [11] column is defined the value by default.
For more information regarding the DS0 programming, see the CONTROL_SMART2IO_PADCONF_2 register in the Control Module /
Control Module Functional Description / Functional Register Description / Signal Integrity Parameter Control Registers With Pad Group
Assignment section of the OMAP4460 TRM.
For more information regarding the load, rise / fall times vs frequency depending the modes (DS0 = 0 or 1) or the supply voltage value
(1.2-V or 1.8-V), see Table 3-4, GPMC DC Electrical Characteristics.
(17) For AE18 / AG12 balls, the hysteresis value is equal to 70 mV minimum for 1.8 V and 60 mV minimum for 1.2 V. For P2 / V2 balls, the
hysteresis value is equal to 70 mV minimum for 1.8 V.
(18) For more information regarding the MIPI D-PHY hysteresis, see Section 3.3.3, Camera DC Electrical Characteristics, Section 3.3.4,
Display DC Electrical Characteristics.
(19) For B5 / B4 balls, the hysteresis is:
– In low-speed and full-speed single-ended receiver modes: minimum 20 mV, typical 50 mV, maximum 80 mV
– In differential receiver modes, no hysteresis feature is present.
(20) vpp must be unconnected. vpp_cust is only powered when programming CPFROM eFuses. Otherwise, it is recommended to leave
vpp_cust turned off (floating). Note that if the TWL6030 PMIC is used then the vpp pulldown resistor inside the TWL6030 must be
disabled when the vpp_cust is turned off.
(21) IO drive strength for usba0_otg_ce pin: minimum 100 µA, maximum 20 mA.
(22) If a CSI2 serial PHY is enabled, vdda_csi2 must be supplied by a dedicated 1.8V low-noise power source.
If a CSI2 serial PHY is definitively disabled, other multiplexed 1.8-V CMOS signals of the interface can be enabled, the interface can be
supplied by the same power source as vdds_1p8v: the vdds_1p8v power source supplies vdda_csi2 ball.
If CSI2 serial PHY and CMOS signals are definitively disabled, the interface balls are left unconnected with its associated power supply
(vdda/vssa) grounded (for circuit reliability reasons).
(23) If a DSI serial PHY is enabled, vdda_dsi must be supplied by a dedicated 1.8-V low-noise power source.
If a DSI serial PHY is definitively disabled, the interface balls are left unconnected and in that case the associated power supply
(vdda/vssa) can be grounded (for circuit reliability reasons) only if the corresponding DSI DPLL is never used to generate the functional
clock to the DISPC.
(24) If the HDMI serial PHY is enabled, vdda_hdmi_vdac must be supplied by a dedicated 1.8-V low-noise power source.
If the HDMI serial PHY is definitively disabled, the interface balls are left unconnected with its associated power supply (vdda/vssa)
grounded (for circuit reliability reasons).
(25) If the HS USB OTG PHY is enabled, vdda_usba0otg_3p3v and vdda_usba0otg_1p8v must be supplied by dedicated 3.3-V and 1.8-V
low-noise power sources.
If the USB OTG PHY is definitively disabled, other multiplexed 3.3V CMOS signals of the interface can be enabled,
vdda_usba0otg_3p3v must be supplied by a dedicated 3.3-V power source and vdda_usba0otg_1p8v can be supplied by the same
power source as vdds_1p8v.
If the USB OTG PHY and CMOS signals are definitively disabled, vdda_usba0otg_3p3v and vdda_usba0otg_1p8v are grounded for
power saving and there is a forward-biased diode from usba0_otg_dp, usba0_otg_dm, usba0_otg_ce pins to vdda_usba0otg_3p3v pin.
(26) If the SDMMC1 functional signals are enabled, vdds_sdmmc1 must be supplied by either dedicated 1.8-V or 3.0-V power source.
If the SDMMC1 functional signals are definitively disabled, other multiplexed 1.8-V CMOS signals of the interface can be enabled, the
interface can be supplied by the same power source as vdds_1p8v: the vdds_1p8v power source supplies vdds_sdmmc1.
If the SDMMC1 functional balls and CMOS signals are definitively disabled, the interface balls are left unconnected and
MMC1_PWRDNZ and MMC1_PBIASLITE_PWRDNZ bits are kept at 0. There are two options for the associated power supply:
– vdds_sdmmc1 is grounded.
– vdds_sdmmc1 is supplied by a 1.8-V or 3.0-V supply. In this case, it is also recommended to keep default value of
MMC1_PBIASLITE_VMODE bit (that is, 1).
For the corresponding setting of the MMC1_PWRDNZ, MMC1_PBIASLITE_PWRDNZ, and MMC1_PBIASLITE_VMODE bits, see the
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Terminal Description
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