OMAP4460 Datasheet, PDF (394/444 Pages) Texas Instruments – Multimedia Device

OMAP4460
Public Version
SWPS046A – JANUARY 2012
www.ti.com
Table 5-230 and Table 5-231 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-138).
Table 5-229. cJTAG Timing Conditions—Normal Mode^(1)(3)(4)
TIMING CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
2
ns
2
ns
Number of external peripherals
1
Far end load
Trace length
30
pF
See⁽²⁾
cm
Characteristics impedance
40
60
Ω
(1) Corresponding balls: AH2 / AG1 / AE3 / AH1 / AE1 / AE2
(2) Maximum PCB trace length = 5 cm and maximum cable = 10 cm
(3) For more information on JTAG ESD guideline example, see Section A.3.2.2.3, ESD Implementation—JTAG and cJTAG Interfaces.
(4) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
Table 5-230. cJTAG Timing Requirements—Normal Mode⁽⁴⁾⁽⁵⁾
NO.
PARAMETER
OPP100, OPP119
MIN
MAX
For MMC PADs
CJ1
CJ2
CJ3
CJ4
1 / t_c(tck)
t_w(tckL)
t_w(tckH)
t_dc(tck)
t_j(tck)
t_{su(tmscV-tckL)}
Frequency⁽¹⁾, input clock jtag_tck
Pulse duration, input clock jtag_tck low
Pulse duration, input clock jtag_tck high
Duty cycle error, input clock jtag_tck
Cycle jitter⁽³⁾, input clock jtag_tck
Setup time, input mode select jtag_tms_tmsc
valid before input clock jtag_tck low
17.5
0.5*P⁽²⁾
0.5*P⁽²⁾
–2857.0 2857.0
–2714.0 2714.0
11.4
CJ5
t_{h(tmscV-tckL)}
Hold time, input mode select jtag_tms_tmsc
4.4
valid after input clock jtag_tck low
For JTAG PADs
CJ1
CJ2
CJ3
CJ4
t_c(tck)
t_w(tckL)
t_w(tckH)
t_dc(tck)
t_j(tck)
t_{su(tmscV-tckL)}
Frequency⁽¹⁾, input clock jtag_tck
Pulse duration, input clock jtag_tck low
Pulse duration, input clock jtag_tck high
Duty cycle error, input clock jtag_tck
Cycle jitter⁽³⁾, input clock jtag_tck
Setup time, input mode select jtag_tms_tmsc
valid before input clock jtag_tck low
20
0.5*P⁽²⁾
0.5*P⁽²⁾
–2500.0 2500.0
–2500.0 2500.0
9.8
CJ5
t_{h(tmscV-tckL)}
Hold time, input mode select jtag_tms_tmsc
3.8
valid after input clock jtag_tck low
(1) Related to the input maximum frequency supported by the JTAG module.
(2) P = jtag_tck period in ns
(3) Maximum cycle jitter supported by jtag_tck input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
(5) See DM Operating Condition Addendum for CORE OPP voltages.
OPP50
MIN
MAX
14
0.5*P⁽²⁾
0.5*P⁽²⁾
–3571.0 3571.0
–3143.0 3143.0
14.5
5.5
19
0.5*P⁽²⁾
0.5*P⁽²⁾
–2632.0 2632.0
–2579.0 2579.0
10.4
4.0
UNIT
MHz
ns
ns
ps
ps
ns
ns
MHz
ns
ns
ps
ps
ns
ns
394 Timing Requirements and Switching Characteristics
Submit Documentation Feedback
Product Folder Link(s): OMAP4460
Copyright © 2012, Texas Instruments Incorporated