OMAP4460 Datasheet, PDF (242/444 Pages) Texas Instruments – Multimedia Device

OMAP4460
Public Version
SWPS046A – JANUARY 2012
www.ti.com
Table 5-20. LPDDR2 Switching Characteristics Correspondence Between Data Manual and LPDDR2
JEDEC Standard—(JESD209-2A)⁽⁴⁾ (continued)
REF.
DD101
DD102
DD200
DD201
DD202
DD203
DD204
DD200b
DD201b
DD202b
DD203b
DD400
DD401
DD401
DD402
DD403
DD404
DD405
DD406
DD407
DD408
DD500
DD501
DD502
DD503
DD504
DD505
DD506
DD507
TIMING PARAMETERS
JEDEC STANDARD PARAMETERS
DESCRIPTION
REF.
DESCRIPTION
t_w(clkL)
Typical pulse duration, lpddr2_ck and lpddr2_nck low t_CL
duration
Average low pulse width
t_sk(clk-Nclk)
t_w(CKE)
Skew , lpddr2_ck edge to opposite lpddr2_nck edge V_IX
Pulse duration, lpddr2_cke high and low duration
t_CKE
Crossing point differential skew
CKE minimum pulse width (high
and low pulse width)
t_d(clkL-CKE)
t_d(clkL-NCS)
t_d(clk-CA)
t_w(CA)
Delay time, lpddr2_ck low to lpddr2_cke
Delay time, lpddr2_ck low to lpddr2_ncs
Delay time, lpddr2_ck low to lpddr2_caz⁽³⁾
Pulse duration, lpddr2_caz⁽³⁾ high and low duration
t_IHCKE /
t_ISCKE
t_IH / t_IS
t_IH / t_IS
t_IPW
CKE input setup / hold time
Address and control input
setup/hold time
Address and control input
setup/hold time
Adress and control input pulse
width
t_cb(clk)
t_db(clkL-CKE)
t_db(clkL-NCS)
t_db(clk-CA)
t_c(DQSO)
t_w(DQSOH)
t_w(DQSOL)
t_{sk(DQSO-NDQSO)}
t_{d(DQSO-DQO/DM)}
t_d(DV-DQSO)
t_d(clkV-DQSO)
t_{d(DQSOHZ-DQSOV)}
t_{d(DQSOV-DQSOHZ)}
t_w(DQO/DM)
Cycle time, lpddr2_ck and lpddr2_nck
Delay time, lpddr2_ck low to lpddr2_cke
Delay time, lpddr2_ck low to lpddr2_ncs
t_CKb
t_ISCKEb /
t_IHCKEb
t_ISb / t_IHb
Delay time, lpddr2_ck low to lpddr2_caz⁽³⁾
t_ISb / t_IHb
Cycle time, lpddr2_dqsx⁽¹⁾ and lpddr2_ndqsx⁽¹⁾
Pulse duration, lpddr2_dqsx⁽¹⁾ and lpddr2_ndqsx⁽¹⁾
high duration
Pulse duration, lpddr2_dqsx⁽¹⁾ and lpddr2_ndqsx⁽¹⁾ low
duration
Skew , lpddr2_dqsx⁽¹⁾ edge to opposite
lpddr2_ndqsx⁽¹⁾ edge
Delay time, lpddr2_dqsx⁽¹⁾ to lpddr2_dqy⁽²⁾ and
lpddr2_dmx⁽¹⁾
Delay time, lpddr2_dqsx⁽¹⁾ valid after lpddr2_ck
transition
Delay time, lpddr2_ck valid to first lpddr2_dqsx⁽¹⁾ edge
t_CK
t_DQSH
t_DQSL
V_IX
t_DS / t_DH
t_DSS / t_DSH
t_DQSS
Delay time, lpddr2_dqsx⁽¹⁾ high impedance to
lpddr2_dqsx⁽¹⁾ valid
Delay time, lpddr2_dqsx⁽¹⁾ last edge to lpddr2_dqsx⁽¹⁾
high impedance state
Pulse duralion, lpddr2_dqy⁽²⁾ and lpddr2_dmx⁽¹⁾ high /
low duration
t_WPRE
t_WPST
t_DIPW
Clock cycle time
CKE input setup/hold time
Address and control input setup /
hold time
Address and control input setup /
hold time
Clock period jitter
DQS input high-level width
DQS input low-level width
Crossing point differential skew
DQ and DM input setup/hold time
DQS falling edge to CK setup /
hold time
Write command to first DQS
latching transition
Write pretamble
Write postamble
DQ qnd DM output pulse width
t_c(ACT-ACT)s
Cycle time, ACTIVE to ACTIVE command
t_RC
ACTIVE to ACTIVE command
period
t_w(SRL)s
Pulse duralion, lpddr2_cke during SELF REFRESH
low duration
t_CKESR
CKE MIN. pulse width during
self-refresh (low pulse width
during self-refresh)
t_c(SR-VAL)s
Cycle time, SELF REFRESH to VALID command
t_XSR
Self refresh exit to next valid
command delay
t_d(DPWDN)s
Delay time, POWER DOWN exit time
t_XP
Exit power down to next valid
command delay
t_d(PWDN)s
t_c(RD-RD)s
t_c(RD-PRE)s
Delay time, DEEP POWER DOWN command
Cycle time, READ to READ command
Cycle time, READ to PRECHARGE command
t_DPD
MINimun deep power down time
t_CCD
LPDDR2-S4 CAS to CAS delay
t_RTP
Internal read to precharge
command delay
t_c(ACT-RD)s
Cycle time, ACTIVE to READ command
t_RCD
RAS to CAS delay
242 Timing Requirements and Switching Characteristics
Submit Documentation Feedback
Product Folder Link(s): OMAP4460
Copyright © 2012, Texas Instruments Incorporated