OMAP4460 Datasheet, PDF (404/444 Pages) Texas Instruments – Multimedia Device

OMAP4460
Public Version
SWPS046A – JANUARY 2012
www.ti.com
Implementation—KeyPAD Interface) and JTAG or cJTAG (Section A.3.2.2.3, ESD
Implementation—JTAG and cJTAG Interfaces) interfaces for specific ESD requirements and
implementation proposals.
• LPDDR2 memory:
– OMAP4 supports two LPDDR2 channels. Each of these channels supports up to two chip selects.
Up to four LPDDR2 memory dies can be connected on top of OMAP4 package via
Package-on-Package implementation. Powers for LPDDR2 memory are connected via feedthrough
in OMAP4460 package.
– The memory component LPDDR2-S4A and LPDDR2-S4B memory have different voltage
requirements. The S4B type needs a single 1.2-V source to supply vdd2 and vddq / vddca.
A.2.2 PCB Power General Routing Guidelines
In this section you will find the necessary steps for the PCB power general routing:
• Section A.2.2.1, Step 1: Requirements and guidelines for PCB stack-up
• Section A.2.2.2, Step 2: Physical layout guidelines of the PDN
• Section A.2.2.3, Step 3: Static IR drop guidelines of PDN. Minimize resistance, avoid neck-down, and
reduce current density.
A.2.2.1 Step 1: PCB Stack-up Guidelines
The PCB stack-up (layer assignment) is an important factor in determining the optimal performance of the
power distribution system. An optimized PCB stack-up for higher power integrity performance can be
achieved by following these requirements:
• Power and ground plane pairs must be closely coupled together. The capacitance formed between the
planes can decouple the power supply at high frequencies. Whenever possible, the power and the
ground planes must be solid to provide continuous return path for return current.
• Use a thin dielectric thickness between the power and ground plane pair. Capacitance is inversely
proportional to the separation of the plane pair. Minimizing the separation distance (the dielectric
thickness) will maximize the capacitance.
• Keep the power and ground plane pair as close as possible to the top and bottom surfaces (see
Figure A-1). This will help in minimizing the decoupling capacitors mounting, via, and the power /
ground plane pair spreading loop inductance.
Trace
Capacitor
Via
3
OMAP DIE
OMAP Package
Power/Ground
Ground/Power
1
2
Note: 1. BGA via pair loop inductance
2. Power/Ground net spreading inductance
3. Capacitor trace inductance
Loop inductance
SWPS040-167
Figure A-1. Minimize Loop Inductance With Proper Layer Assignment
The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a
404 OMAP4460 Processor Multimedia Device PCB Guideline
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