OMAP4460 Datasheet, PDF (264/444 Pages) Texas Instruments – Multimedia Device

OMAP4460
Public Version
SWPS046A – JANUARY 2012
www.ti.com
McBSP supports two types of data transfer at the system level:
• The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge
and captured on the same edge (one clock period later).
• The half-cycle mode, for which one-half clock period is used to transfer the data, generated on one
edge and captured on the opposite edge (one-half clock period later). Note that a new data is
generated only every clock period, which secures the required hold time.
The interface clock (clkX/CLKR) activation edge (data/frame sync capture and generation) has to be
configured accordingly with the external peripheral (activation edge capability) and the type of data
transfer required at the system level.
Depending on the number of pins, McBSP supports either:
• 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.
• 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are
internally looped back, via software configuration, respectively to the clkr and fsr internal signals for
data receive.
5.6.1.1 McBSP1, McBSP2, and McBSP3 Set#1
5.6.1.1.1 McBSP1, McBSP2, and McBSP3 Set#1—I2S/PCM
Table 5-42 through Table 5-45 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-57 and Figure 5-58).
Table 5-41. McBSP1, 2 Timing Conditions—I2S/PCM^(1)(2)(3)
SYSTEM CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
400
6500
ps
400
6500
ps
Number of external peripherals
1
Far end load
5
pF
Trace length
9
cm
Characteristics impedance
30
55
Ω
(1) IO settings: MB[1:0] = 10 and LB0 = 0.
For more information, see Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment / 50-Ω Output Buffer I/Os with Combined Mode and Load Settings section of
the OMAP4460 TRM.
(2) In this table the rise and fall times are calculated for 10% to 90% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(3) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
5.6.1.1.1.1 McBSP1 and McBSP2—I2S/PCM Full and Half Cycle—Master Mode—24 MHz
Table 5-42. McBSP1, 2 Timing Requirements—I2S/PCM—Master Mode^(1)(3)(6)
NO.
1 / t_c(clks)
t_w(clksL)
t_w(clksH)
t_dc(clks)
PARAMETER
Frequency, input abe_clks⁽⁵⁾ clock
Typical pulse duration, input abe_clks low
Typical pulse duration, output abe_clks high
Duty cycle error, input abe_clks
OPP100, OPP119
MIN
MAX
24.576⁽⁵⁾
0.5 * P⁽⁴⁾
0.5 * P⁽⁴⁾
–0.05 *
0.05 *
P⁽⁴⁾ + 610 P⁽⁴⁾ – 610
OPP50
MIN
MAX
12.288⁽⁵⁾
0.5 * P⁽⁴⁾
0.5 * P⁽⁴⁾
–0.05 *
0.05 *
P⁽⁴⁾ + 610 P⁽⁴⁾ – 610
UNIT
MHz
ns
ns
ps
264 Timing Requirements and Switching Characteristics
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