OMAP4460 Datasheet, PDF (135/444 Pages) Texas Instruments – Multimedia Device

Public Version
OMAP4460
www.ti.com
SWPS046A – JANUARY 2012
Table 3-5. LPDDR2 DC Electrical Characteristics (continued)
PARAMETER
MIN
NOM
MAX
UNIT
Z_O
Output impedance
i[2:0] = 000 (Drv5)
1.66 * R_REF
Ω
i[2:0] = 001 (Drv6)
1.33 * R_REF
i[2:0] = 010 (Drv7)
i[2:0] = 011 (Drv8)
1.14 * R_REF
R_REF(2)
i[2:0] = 100 (Drv9)
0.88 * R_REF
i[2:0] = 101 (Drv10)
0.8 * R_REF
i[2:0] = 110 (Drv11)
0.73 * R_REF
i[2:0] = 111 (Drv12)
0.67 * R_REF
t_OT
Output transition
sr[1:0] = 00 (Fastest)
250
ps
time/turn-on time (rise time,
t_R or fall time, t_F) measured
sr[1:0] = 01 (Faster)
315
between 10% to 90% of
sr[1:0] = 10 (Fast)
340
PAD voltage^(3)(4)(6)
sr[1:0] = 11 (Slow)
390
Maximum noise on the IO
supply voltage^(3)(5)(6)
sr[1:0] = 00 (Fastest)
sr[1:0] = 01 (Faster)
215
mV_PP
110
sr[1:0] = 10 (Fast)
108
sr[1:0] = 11 (Slow)
110
Signals in Mode 0: lpddr21_vref_ca, lpddr21_vref_dq, lpddr22_vref_ca, lpddr22_vref_dq
(Top Balls: AH16 / B15 / U28 / R2)
V_REF
Reference generation dc
voltage level
vref_tap[1:0] = 00
(Mint_2ua mode)
0.495 *
0.500 *
0.505 *
V
vddy_vref_lpddr2⁽⁸⁾ vddy_vref_ vddy_vref_lpddr2⁽⁸⁾
lpddr2⁽⁸⁾
vref_tap[1:0] = 01
(Mint_4ua mode)
0.492 *
vddy_vref_lpddr2⁽⁸⁾
0.500 *
vddy_vref_
lpddr2⁽⁸⁾
0.508 *
vddy_vref_lpddr2⁽⁸⁾
vref_tap[1:0] = 10
(Mint_6ua mode)
0.490 *
vddy_vref_lpddr2⁽⁸⁾
0.500 *
vddy_vref_
lpddr2⁽⁸⁾
0.510 *
vddy_vref_lpddr2⁽⁸⁾
vref_tap[1:0] = 11
(Mint_8ua mode)
0.490 *
vddy_vref_lpddr2⁽⁸⁾
0.500 *
vddy_vref_
lpddr2⁽⁸⁾
0.510 *
vddy_vref_lpddr2⁽⁸⁾
(1) This buffer is designed for high-speed application. In high-speed mode, it is fast enough to avoid any noise on the signal during
transition and then hysteresis is not required.
(2) R_REF (reference output impedance) is considered to be the production trimming setting for Drv8 mode, with R_REF = 50 Ω, which
corresponds to Z_O = 50 Ω (I_OUT = 8 mA). For a full description of the output impedance setting, see the the Control Module / Control
Module Functional Description / Functional Register Description / Signal Integrity Parameter Control Registers With Pad Group
Assignment section of the OMAP4460 TRM.
(3) To achieve optimal noise/speed trade off, the slew rate (turn-on time) of the output signal can be programmed using the slew rate
control bits sr[1:0]. Please note that the control bits sr[1:0] do not affect the driver DC drive-strength. They only control the driver turn-on
time. It is to be noted that turn-on time and maximum supply noise are the parameter defined to help user make relative comparison and
correlate the driver operation at different turn-on time settings.
(4) Output transition time/turn-on time for Drv8 setting, i[2:0] = 011. For a full description of this setting, see the Control Module / Control
Module Functional Description / Functional Register Description / Signal Integrity Parameter Control Registers With Pad Group
Assignment section of the OMAP4460 TRM.
(5) Maximum noise (peak-peak) on the IO supply voltage for Drv8 setting, i[2:0] = 011.
(6) The measurement setup (see Figure 3-1 and Figure 3-2) is not intended as a precise representation of any particular system
environment or a depiction of the actual load presented. Maximum output supply noise (see Figure 3-2, L*di/dt) on the IO supply is
measured with 1 nH of inductance on the IO supply.
(7) vddx_lpddr2 can have the value vddq_lpddr2, vddca_lpddr21, vddca_lpddr22 depending on the ball used. For more information of the
power supply name and the corresponding pin, ball, see the POWER [9] column of Table 2-1.
(8) vddy_vref_lpddr2 can have the value vddca_vref_lpddr21, vddca_lpddr22, vddq_vref_lpddr21, vddq_vref_lpddr22 depending on the ball
used. For more information of the power supply name and the corresponding pin, ball, see the POWER [9] column of Table 2-1.
Copyright © 2012, Texas Instruments Incorporated
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Electrical Characteristics 135