OMAP4460 Datasheet, PDF (284/444 Pages) Texas Instruments – Multimedia Device

OMAP4460
Public Version
SWPS046A – JANUARY 2012
Table 5-68. McBSP4 Switching Characteristics—I2S/PCM—Master Mode⁽⁴⁾⁽⁸⁾
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NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
BM0
BM1
BM2
1 / t_c(clk)
t_w(clkL)
t_w(clkH)
Frequency⁽¹⁾, output mcbsp4_clk clock
Typical pulse duration, output mcbsp4_clk low
Typical pulse duration, output mcbsp4_clk
high
MIN
MAX
24⁽⁷⁾
0.5*P⁽²⁾
0.5*P⁽²⁾
MIN
MAX
12⁽⁷⁾
0.5*P⁽²⁾
0.5*P⁽²⁾
MHz
ns
ns
t_dc(clk)
t_j(clk)
Duty cycle error, output mcbsp4_clk
–2035
2035
–4069
4069
ps
Jitter standard deviation⁽³⁾, output mcbsp4_clk
65
65
ps
t_R(clk)
Rise time, output mcbsp4_clk
400
6500
400
6500
ps
t_F(clk)
Fall time, output mcbsp4_clk
400
6500
400
6500
ps
BM3
t_d(clkAE-fsV)
Delay time, output mcbsp4_clk active edge to
–7.1
11.7
–15.2
23.6
ns
output mcbsp4_fs⁽⁶⁾ valid
BM4
t_{d(clkxAE-dxV)}
Delay time, output mcbsp4_clkx active edge to –7.1
11.7
–15.2
23.6
ns
output mcbsp4_dx valid
t_R(fs)
t_F(fs)
Rise time, output mcbsp4_fs⁽⁶⁾
Fall time, output mcbsp4_fs⁽⁶⁾
400
6500
400
6500
ps
400
6500
400
6500
ps
t_R(dx)
Rise time, output mcbsp4_dx
400
6500
400
6500
ps
t_F(dx)
Fall time, output mcbsp4_dx
400
6500
400
6500
ps
(1) Related to the output mcbsp4_clkx / mcbsp4_clkr maximum and minimum frequency programmable in McBSP module by setting the
configuration register SRGR1_REG[7..0].
For more information regarding the registers configuration see the Serial Communication Interface / Multichannel Buffered Serial Port
(McBSP) / MCBSP Register Manual / MCBSP Registers / MCBSP Register Summary Table section of the OMAP4460 TRM.
(2) P = mcbsp4_clkx / mcbsp4_clkr output clk period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
(4) The timings apply to all configurations regardless of mcbsp4_clk polarity and which clock edges are used to drive output data and
capture input data.
(5) mcbsp4_clk corresponds to either mcbsp4_clkx or mcbsp4_clkr; mcbsp4_clkr is available in 6-pin mode only.
(6) mcbsp4_fs corresponds to either mcbsp4_fsx or mcbsp4_fsr; mcbsp4_fsr is available in 6-pin mode only.
(7) This McBSP4 output clock frequency is based on an output PER DPLL configured at 96 MHz.
For more information regarding the registers configuration, see the Power, Reset and Clock Management / Clock Management
Functional Description / Internal Clock Sources/Generators / DPLL_PER Description section of the OMAP4460 TRM.
(8) See DM Operating Condition Addendum for CORE OPP voltages.
5.6.1.3.2.2 McBSP4—I2S/PCM—Half-Cycle—12-MHz Slave Mode
Table 5-69. McBSP4 Timing Requirements—I2S/PCM—Slave Mode^(4)(5)(8)
NO.
BS0
BS1
BS2
BS3
BS4
BS6
BS7
1 / t_c(clk)
t_w(clkL)
t_w(clkH)
t_dc(clk)
t_j(clk)
t_{su(fsV-clkAE)}
t_h(clkAE-fsV)
t_{su(drV-clkAE)}
t_h(clkAE-drV)
PARAMETER
Frequency⁽¹⁾, mcbsp4_clk⁽⁶⁾
Typical pulse duration, mcbsp4_clk⁽⁶⁾ low
Typical pulse duration, mcbsp4_clk⁽⁶⁾ high
Duty cycle error, mcbsp4_clk⁽⁶⁾
Cycle jitter⁽³⁾, mcbsp4_clk⁽⁶⁾
Setup time, mcbsp4_fs⁽⁷⁾ valid before
mcbsp4_clk⁽⁶⁾ active edge
Hold time, mcbsp4_fs⁽⁷⁾ valid after
mcbsp4_clk⁽⁶⁾ active edge
Setup time, mcbsp4_dr valid before
mcbsp4_clk⁽⁶⁾ active edge
Hold time, mcbsp4_dr valid after
mcbsp4_clk⁽⁶⁾ active edge
OPP100, OPP119
MIN
MAX
12
0.5*P⁽²⁾
0.5*P⁽²⁾
–4069
4069
2000
13.2
0.3
13.2
0.3
OPP50
MIN
MAX
6
0.5*P⁽²⁾
0.5*P⁽²⁾
–8138
8138
2000
26.7
0.3
26.7
0.3
UNIT
MHz
ns
ns
ps
ps
ns
ns
ns
ns
284 Timing Requirements and Switching Characteristics
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