OMAP4460 Datasheet, PDF (189/444 Pages) Texas Instruments – Multimedia Device

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OMAP4460
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SWPS046A – JANUARY 2012
Table 4-7. fref_xtal_in Squarer Input Clock Timing Requirements—Bypass Mode⁽³⁾ (continued)
NAME
t_j(xtalin)
DESCRIPTION
Peak-to-peak jitter⁽¹⁾, fref_xtal_in
MIN
TYP
MAX
UNIT
1% * t_c(XTALIN)(5) (ps) *
ps
Xdiv⁽⁴⁾ – 210 (ps)
t_R(xtalin)
t_F(xtalin)
t_j(xtalin)
Rise time, fref_xtal_in
Fall time, fref_xtal_in
Frequency stability, fref_xtal_in
5
5
50 (±5)⁽²⁾
ns
ns
ppm
(1) Peak-to-peak jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
Maximum and minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock
period.
(2) ±50 ppm is the clock frequency stability/accuracy and ±5 ppm takes into account the aging effects.
(3) In this table the rise and fall times are calculated for 10% to 90% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(4) In Xdiv, Xdiv represents the internal DSS DPLLs dividers. [t_c(XTALIN) (ps) * Xdiv] or [t_c(SLICER) (ps) * Xdiv] represents the input clock cycle
coming to the DSS DPLLs (that means after dividing). For the other internal DPLLs, the Xdiv value is equal to 1. This input jitter
limitation comes from the DPLL constraint shifted at ball level. To clarify this formula, please consider a maximum jitter of 1% of the
clock period coming to the internal DPLL (input DPLL).
For more information, see the Power, Reset and Clock Management / Clock Management Functional Description / Internal Clock
Sources/Generators / PRM Clock Source section of the OMAP4460 TRM.
(5) t_c(XTALIN) is the fref_xtal_in cycle time of the clock coming to fref_xtalin_in ball.
fref_xtal_in
OSC0
OSC1
Figure 4-4. fref_xtal_in Squarer Input Clock
OSC1
SWPS039-007
4.1.4 fref_slicer_in Input Clock
Table 4-8 summarizes the electrical characteristics of the fref_slicer_in input clock.
Table 4-8. fref_slicer_in Input Clock Electrical Characteristics
NAME
f
C_i
R_i
DESCRIPTION
Frequency, fref_slicer_in
Input capacitance
Input resistance
MIN
TYP
MAX
12, 16.8, 19.2, 26, and 38.4
2.5
14
29
Table 4-9 details the input requirements of the fref_slicer_in input clock.
Table 4-9. fref_slicer_in Input Square Clock Timing Requirements⁽¹⁾⁽⁶⁾
UNIT
MHz
pF
kΩ
NAME
SLC0
SLC1
1 / t_{c(fref_slicer_in)}
t_{w(fref_slicer_in)}
t_{j(fref_slicer_in)}
DESCRIPTION
Frequency, fref_slicer_in
Pulse duration, fref_slicer_in low or
high
Peak-to-peak jitter⁽²⁾, fref_slicer_in
Active mode
Square Clock
Bypass mode
Square Clock
Active mode
Square Clock
Bypass mode
Square Clock
t_{R(fref_slicer_in)} Rise time, fref_slicer_in
MIN
TYP
MAX
12, 16.8, 19.2, 26, and 38.4
0.45 * t_c(SLICER)
0.55 * t_c(SLICER)
UNIT
MHz
ns
0.47 * t_c(SLICER)
1.5
0.53 * t_c(SLICER)
1% * t_c(SLICER)(4)
ps
(ps) * Xdiv⁽³⁾ – 200
(ps)
1% * t_c(SLICER)(4)
(ps) * Xdiv⁽³⁾ – 250
(ps)
10
ns
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Clock Specifications 189