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OMAP4460 Datasheet, PDF (376/444 Pages) Texas Instruments – Multimedia Device
OMAP4460
Public Version
SWPS046A – JANUARY 2012
(6) See DM Operating Condition Addendum for CORE OPP voltages.
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MMC1
MMC2
MMC2
sdmmc2_clk
MMC5
MMC5
sdmmc2_cmd
MMC6
MMC6
sdmmc2_dat[n:0]
SWPS040-081
Figure 5-121. MMC/SD/SDIO 2 Interface—High-Speed SDR JC64—Transmitter Mode(1)(2)
(1) In sdmmc2_dat[n:0], n up to 7
(2) In this section, the MMC/SD/SDIO output data and command signals are driven on the falling clock edge.
In this case, the MMCHS_HCTL[2] HSPE bit is set to 0. The controller is by default in this mode to maximize hold timings.
For more information, see MMC/SD/SDIO / MMC/SD/SDIO Functional Description / Output Signals Generation / Generation on Falling
Edge of MMC Clock section of the OMAP4460 TRM.
MMC1
MMC2
MMC2
sdmmc2_clk
MMC3
MMC4
sdmmc2_cmd
MMC7
MMC8
sdmmc2_dat[n:0]
SWPS040-082
Figure 5-122. MMC/SD/SDIO 2 Interface—High-Speed SDR JC64—Receiver Mode(1)
(1) In sdmmc2_dat[n:0], n up to 7
5.7.1.2.2 MMC/SD/SDIO 2 Interface—eMMC—High-Speed DDR JC64 Mode
Table 5-205 and Table 5-206 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-123 and Figure 5-124).
Table 5-204. MMC/SD/SDIO 2 Interface Timing Conditions—High-Speed DDR JC64 Mode(1)(2)(3)(4)(5)
TIMING CONDITION PARAMETER
For Balls: AE5 / AF5 / AE4 / AF4 / AG3 / AF3 / AD2 / AD3 / AD4 / AC2 (Mux Mode 5)
Input Conditions
tR
Input command signal rise time
tF
Input command signal fall time
tR
Input data signal rise time
tF
Input data signal fall time
For Balls: C12 / D12 / C13 / D13 / C15 / D15 / A16 / B16 / B11 / B12 (Mux Mode 1)
Input Conditions
tR
Input command signal rise time
tF
Input command signal fall time
tR
Input data signal rise time
tF
Input data signal fall time
PCB Conditions
VALUE
MIN
MAX
UNIT
0.15
0.98
ns
0.15
0.98
ns
0.15
0.98
ns
0.15
0.98
ns
0.11
1.01
ns
0.12
1.01
ns
0.11
1.01
ns
0.12
1.01
ns
376 Timing Requirements and Switching Characteristics
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