OMAP4460 Datasheet, PDF (343/444 Pages) Texas Instruments – Multimedia Device

Public Version
OMAP4460
www.ti.com
SWPS046A – JANUARY 2012
(2) In this table the rise and fall times are calculated for 10% to 90% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(3) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
Table 5-163. Low- / Full-Speed USBB2 Timing Requirements—Bidirectional TLL 3-pin Mode—1.8 V⁽¹⁾⁽²⁾
NO.
PARAMETER
OPP100, OPP119
OPP50
MIN
MAX
MIN
MAX
FSU17
t_d(DAT,SE0)
Time duration, usbb2_mm_txdat and
usbb2_mm_txse0 low together during
transition
14.0
14.0
FSU18
t_d(DAT,SE0)
Time duration, usbb2_mm_txdat and
usbb2_mm_txse0 high together during
transition
8.0
8.0
(1) See DM Operating Condition Addendum for CORE OPP voltages.
(2) Low-Speed mode is a subset of the Full-Speed mode and it is expected to work at low bandwidth (1.5Mb/s).
UNIT
ns
ns
Table 5-164. Low- / Full-Speed USBB2 Switching Characteristics—Bidirectional TLL 3-pin Mode—1.8
V⁽¹⁾⁽²⁾
NO.
PARAMETER
OPP100, OPP119
OPP50
MIN
MAX
MIN
MAX
FSU19
t_{d(TXENL-DATV)}
Delay time usbb2_mm_txen low to
usbb2_mm_txdat valid
81.8
84.8
81.8
84.8
FSU20
t_{d(TXENL-SE0V)}
Delay time usbb2_mm_txen low to
usbb2_mm_txse0 valid
81.8
84.8
81.8
84.8
FSU21
t_sk(DAT-SE0)
Skew between usbb2_mm_txdat and
usbb2_mm_txse0 transition
1.5
1.5
FSU22
t_{d(DATV-TXENH)}
Delay time, usbb2_mm_txdat invalid before
usbb2_mm_txen high
81.8
81.8
FSU23
t_{d(SE0V-TXENH)}
Delay time, usbb2_mm_txse0 invalid before
usbb2_mm_txen high
81.8
81.8
(1) See DM Operating Condition Addendum for CORE OPP voltages.
(2) Low-Speed mode is a subset of the Full-Speed mode and it is expected to work at low bandwidth (1.5Mb/s).
UNIT
ns
ns
ns
ns
ns
usbb2_mm_txen
usbb2_mm_txdat
FSU19
Transmit
FSU22
Receive
FSU17
FSU18
usbb2_mm_txse0
FSU20
FSU21
FSU23
FSU17
FSU18
SWPS040-141
Figure 5-96. Low- / Full-Speed USBB2—Bidirectional TLL 3-pin Mode—1.8 V
5.6.8.4.5 Low- / Full-Speed USBB2 (FSUSB)—Bidirectional Standard 2-pin Mode
Table 5-166 assumes testing over the recommended operating conditions and electrical characteristic
conditions below (see Figure 5-97).
Table 5-165. Low- / Full-Speed USBB2 Timing Conditions—Bidirectional 2-pin Mode—1.8 V^(1)(2)(3)
Input Conditions
TIMING CONDITION PARAMETER
VALUE
MIN
MAX
UNIT
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Timing Requirements and Switching Characteristics 343
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