OMAP4460 Datasheet, PDF (225/444 Pages) Texas Instruments – Multimedia Device

Public Version
OMAP4460
www.ti.com
SWPS046A – JANUARY 2012
(1) IO settings except gpmc_nwp: LB0 = 1.
For more information, see the Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment section of the OMAP4460 TRM.
IO settings for gpmc_nwp: MB[1:0] = 01 and LB0 = 0.
For more information, see the Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment / 50-Ω Output Buffer I/Os with Combined Mode and Load Settings section of
the OMAP4460 TRM.
(2) In this table the rise and fall times are calculated for 20% to 80% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(3) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
Table 5-13. GPMC/NAND—Asynchronous Mode—Internal Parameters
NO.
GNFI1
GNFI2
GNFI3
GNFI4
GNFI5
GNFI6
GNFI7
GNFI8
PARAMETER
Maximum output data generation delay from internal functional
clock
Maximum input data capture delay by internal functional clock
Maximum chip select generation delay from internal functional
clock
Maximum address latch enable generation delay from internal
functional clock
Maximum command latch enable generation delay from
internal functional clock
Maximum output enable generation delay from internal
functional clock
Maximum write enable generation delay from internal
functional clock
Maximum functional clock skew
OPP100, OPP119
MIN
MAX
6.5
4.0
6.5
6.5
6.5
6.5
6.5
100.0
OPP50
MIN
MAX
13.7
8.1
13.7
13.7
13.7
13.7
13.7
200.0
UNIT
ns
ns
ns
ns
ns
ns
ns
ps
Table 5-14. GPMC/NAND Flash Timing Requirements—Asynchronous Mode⁽¹⁾⁽²⁾
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
GNF12
t_ACc(DAT) Data maximum access time
MIN
MAX
MIN
MAX
J⁽¹⁰⁾
J⁽¹⁰⁾
GPMC_
FCLK
cycles
(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) See DM Operating Condition Addendum for CORE OPP voltages.
Table 5-15. GPMC/NAND Flash Switching Characteristics—Asynchronous Mode
NO.
GNF0
GNF1
GNF2
GNF3
GNF4
t_R(DO)
t_F(DO)
t_w(nWEV)
t_d(nCSV-nWEV)
t_d(CLEH-nWEV)
t_d(nWEV-DV)
t_d(nWEIV-DIV)
PARAMETER
Rise time, output data
Fall time, output data
Pulse duration, gpmc_nwe valid time
Delay time, gpmc_ncsx valid to
gpmc_nwe valid
Delay time, gpmc_nbe0_cle high to
gpmc_nwe valid
Delay time, gpmc_d[15:0] valid to
gpmc_nwe valid
Delay time, gpmc_nwe invalid to
gpmc_d[15:0] invalid
OPP100, OPP119
MIN
MAX
2
2
A⁽¹⁾
B⁽²⁾ – 0.2 B⁽²⁾ + 2.0
C⁽³⁾ – 0.2 C⁽³⁾ + 2.0
D⁽⁴⁾ – 0.2 D⁽⁴⁾ + 2.0
E⁽⁵⁾ – 0.2 E⁽⁵⁾ + 2.0
OPP50
MIN
MAX
2
2
A⁽¹⁾
B⁽²⁾ – 0.2 B⁽²⁾ + 3.7
C⁽³⁾ – 0.2 C⁽³⁾ + 3.7
D⁽⁴⁾ – 0.2 D⁽⁴⁾ + 3.7
E⁽⁵⁾ – 0.2 E⁽⁵⁾ + 3.7
UNIT
ns
ns
ns
ns
ns
ns
ns
Copyright © 2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 225
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