OMAP4460 Datasheet, PDF (282/444 Pages) Texas Instruments – Multimedia Device

OMAP4460
Public Version
SWPS046A – JANUARY 2012
www.ti.com
Table 5-63. McBSP4 Switching Characteristics—I2S/PCM—Master Mode⁽⁴⁾⁽⁸⁾ (continued)
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
MIN
MAX
MIN
MAX
BM3
t_d(clkAE-fsV)
Delay time, output mcbsp4_clk⁽⁵⁾ active edge
0.6
9.4
0.9
19.5
ns
to output mcbsp4_fs⁽⁶⁾ valid
BM4
t_{d(clkxAE-dxV)}
Delay time, output mcbsp4_clkx active edge to 0.6
9.4
0.9
19.5
ns
output mcbsp4_dx valid
t_R(fs)
t_F(fs)
Rise time, output mcbsp4_fs⁽⁶⁾
Fall time, output mcbsp4_fs⁽⁶⁾
400
4000
400
4000
ps
400
4000
400
4000
ps
t_R(dx)
Rise time, output mcbsp4_dx
400
4000
400
4000
ps
t_F(dx)
Fall time, output mcbsp4_dx
400
4000
400
4000
ps
(1) Related to the output mcbsp4_clkx / mcbsp4_clkr maximum and minimum frequency programmable in McBSP module by setting the
configuration register SRGR1_REG[7..0].
For more information regarding the registers configuration see Serial Communication Interface / Multichannel Buffered Serial Port
(McBSP) / MCBSP Register Manual / MCBSP Registers / MCBSP Register Summary Table section of the OMAP4460 TRM.
(2) P = mcbsp4_clkx / mcbsp4_clkr output clk period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
(4) The timings apply to all configurations regardless of mcbsp4_clk polarity and which clock edges are used to drive output data and
capture input data.
(5) mcbsp4_clk corresponds to either mcbsp4_clkx or mcbsp4_clkr; mcbsp4_clkr is available in 6-pin mode only.
(6) mcbsp4_fs corresponds to either mcbsp4_fsx or mcbsp4_fsr; mcbsp4_fsr is available in 6-pin mode only.
(7) This McBSP4 output clock frequency is based on an output PER DPLL configured at 96 MHz.
For more information regarding the registers configuration, see Power, Reset and Clock Management / Clock Management Functional
Description / Internal Clock Sources/Generators / DPLL_PER Description section of the OMAP4460 TRM.
(8) See DM Operating Condition Addendum for CORE OPP voltages.
5.6.1.3.1.2 McBSP4—I2S/PCM—Full Cycle—24-MHz Slave Mode
Table 5-64. McBSP4 Timing Requirements—I2S/PCM—Slave Mode^(4)(5)(8)
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
BS0
BS1
BS2
BS3
BS4
1 / t_c(clk)
t_w(clkL)
t_w(clkH)
t_dc(clk)
t_j(clk)
t_{su(fsV-clkAE)}
t_h(clkAE-fsV)
Frequency⁽¹⁾, mcbsp4_clk⁽⁶⁾
Typical pulse duration, mcbsp4_clk⁽⁶⁾ low
Typical pulse duration, mcbsp4_clk⁽⁶⁾ high
Duty cycle error, mcbsp4_clk⁽⁶⁾
Cycle jitter⁽³⁾, mcbsp4_clk⁽⁶⁾
Setup time, mcbsp4_fs⁽⁷⁾ valid before
mcbsp4_clk⁽⁶⁾ active edge
Hold time, mcbsp4_fs⁽⁷⁾ valid after
mcbsp4_clk⁽⁶⁾ active edge
MIN
MAX
24
0.5*P⁽²⁾
0.5*P⁽²⁾
–2035
2035
1221
6.0
0.2
MIN
MAX
12
0.5*P⁽²⁾
0.5*P⁽²⁾
–4069
4069
2000
11.9
0.3
MHz
ns
ns
ps
ps
ns
ns
BS6
t_{su(drV-clkAE)}
Setup time, mcbsp4_dr valid before
6.0
11.9
ns
mcbsp4_clk⁽⁶⁾ active edge
BS7
t_h(clkAE-drV)
Hold time, mcbsp4_dr valid after
0.2
0.3
ns
mcbsp4_clk⁽⁶⁾ active edge
(1) Related to the input maximum frequency supported by the McBSP module.
(2) P = mcbsp4_clkx / mcbsp4_clkr period in ns
(3) Maximum cycle jitter supported by mcbsp4_clkx / mcbsp4_clkr input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
(5) The timings apply to all configurations regardless of mcbsp4_clk polarity and which clock edges are used to drive output data and
capture input data.
(6) mcbsp4_clk corresponds to either mcbsp4_clkx or mcbsp4_clkr; mcbsp4_clkr is available in 6-pin mode only.
(7) mcbsp4_fs corresponds to either mcbsp4_fsx or mcbsp4_fsr; mcbsp4_fsr is available in 6-pin mode only.
(8) See DM Operating Condition Addendum for CORE OPP voltages.
282 Timing Requirements and Switching Characteristics
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