OMAP4460 Datasheet, PDF (313/444 Pages) Texas Instruments – Multimedia Device

Public Version
OMAP4460
www.ti.com
SWPS046A – JANUARY 2012
SB2 SB3
SB1
SLIMBUS_CLK
SB6
SLIMBUS_DATA
Figure 5-77. ABE SlimBus1, SlimBus2 Master Write Mode⁽¹⁾⁽²⁾
SWPS040-150
(1) The polarity of signals is software configurable.
For more information, see the Serial Communication Interface / Serial Low-Power Inter-Chip Media Bus Controller section of the
OMAP4460 TRM.
(2) slimbusx represents abe_slimbus1 and slimbus2.
5.6.6.2 ABE SlimBus1, SlimBus2—SLIMBUS SDR 19.2 MHz
Table 5-107 and Table 5-108 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-78 and Figure 5-79).
Table 5-106. ABE SlimBus1, SlimBus2 Timing Conditions^(1)(2)(3)
SYSTEM CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
1.20
ps
1.20
ps
Number of external peripherals
4
Far end load
20
pF
Trace length
10
cm
Characteristics impedance
30
60
Ω
(1) IO settings: MB[1:0] = 11 and LB0 = 1.
– Balls: AC26 / AC25 / AG24 / AH24 (abe_slimbus1_clock, abe_slimbus1_data, slimbus2_clock, slimbus2_data)
For more information on IO settings, see Control Module / Control Module Functional Description/ Functional Register Description /
Signal Integrity Parameter Control Registers with Pad Group Assignment / 50-Ω Output Buffer I/Os with Combined Mode and Load
Settings section of the OMAP4460 TRM.
– Corresponding voltage: 1.8 V.
(2) In this table the rise and fall times are calculated for 20% to 80% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(3) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
Table 5-107. ABE SlimBus1, SlimBus2 Timing Requirements⁽⁴⁾⁽⁶⁾
NO.
SB1
SB2
SB3
SB4
SB5
1 / t_c(clk)
t_w(clkH)
t_w(clkL)
t_dc(clk)
t_j(clk)
t_su(dV-clkH)
t_h(clkH-dV)
PARAMETER
Frequency⁽¹⁾ slimbusx_clock clock period
Typical pulse duration, slimbusx_clock clock low
Typical pulse duration, slimbusx_clock clock high
Duty cycle slimbusx_clock clock error
Cycle slimbusx_clock clock jitter⁽³⁾
Setup time, slimbusx_data valid before slimbusx_clock
falling edge
Hold time, slimbusx_data valid after slimbusx_clock
falling edge
OPP100, OPP119
MIN
MAX
19.2
0.5*P⁽²⁾
0.5*P⁽²⁾
2000
283
4.6
0.2
OPP50
MIN
MAX
9.6
0.5*P⁽²⁾
0.5*P⁽²⁾
2000
283
8.1
2.2
UNIT
MHz
ns
ns
ps
ps
ns
ns
Copyright © 2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 313
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