OMAP4460 Datasheet, PDF (271/444 Pages) Texas Instruments – Multimedia Device

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OMAP4460
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SWPS046A – JANUARY 2012
abe_mcbspx_clk
BM0
BM1 BM2
abe_mcbspx_fs
BM3
BM3
abe_mcbspx_dx
abe_mcbspx_dr
BM4
DX7
BM5
DR7
BM4
DX6
BM6
DR6
BM4
DX0
DR0
SWPS040-108
Figure 5-59. McBSP1, 2, and 3 Set#1—TDM / Half-Cycle—Master Mode^{(1)(2)(3)(4)(5)(6)}
(1) abe_mcbspx_clk corresponds to either abe_mcbspx_clkx or abe_mcbspx_clkr; abe_mcbspx_fs corresponds to either abe_mcbspx_fsx
or abe_mcbspx_fsr.
McBSP in 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.
McBSP in 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are internally looped back, via
software configuration, respectively to the clkr and fsr internal signals for data receive.
(2) The polarity of McBSP frame synchronization is software configurable.
(3) The active clock edge selection of abe_mcbspx_clk (rising or falling) on which abe_mcbspx_dx data is latched and abe_mcbspx_dr data
is sampled is software configurable.
(4) Timing diagrams are for data delay set to 1.
(5) For more information regarding the registers configuration see the Serial Communication Interface / Multichannel Buffered Serial Port
(McBSP) / MCBSP Register Manual / MCBSP Registers / MCBSP Register Summary Table section of the OMAP4460 TRM.
(6) In abe_mcbspx, x is equal to 1, 2, or 3 Set#1 (Balls: AG25, AF25, AE25, AF26).
BS0
abe_mcbspx_clk
BS1 BS2
abe_mcbspx_fs
BS3
BS4
abe_mcbspx_dx
abe_mcbspx_dr
BS5
BS5
BS5
DX7
DX6
BS7
BS6
DR7
DR6
DX0
DR0
SWPS040-109
Figure 5-60. McBSP1, 2, and 3 Set#1—TDM / Half-Cycle—Slave Mode^{(1)(2)(3)(4)(5)(6)}
(1) abe_mcbspx_clk corresponds to either abe_mcbspx_clkx or abe_mcbspx_clkr; abe_mcbspx_fs corresponds to either abe_mcbspx_fsx
or abe_mcbspx_fsr.
McBSP in 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.
McBSP in 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are internally looped back, via
software configuration, respectively to the clkr and fsr internal signals for data receive.
(2) The polarity of McBSP frame synchronization is software configurable.
(3) The active clock edge selection of abe_mcbspx_clk (rising or falling) on which abe_mcbspx_dx data is latched and abe_mcbspx_dr data
is sampled is software configurable.
(4) Timing diagrams are for data delay set to 1.
(5) For more information regarding the registers configuration see the Serial Communication Interface / Multichannel Buffered Serial Port
(McBSP) / MCBSP Register Manual / MCBSP Registers / MCBSP Register Summary Table section of the OMAP4460 TRM.
(6) In abe_mcbspx, x is equal to 1, 2, or 3 Set#1 (Balls: AG25, AF25, AE25, AF26).
Copyright © 2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 271
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