TIC10024-Q1 Datasheet, PDF (64/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

TIC10024-Q1
SCPS268 – SEPTEMBER 2017
www.ti.com
9.4.16 INT_EN_CFG0 Register (Offset = 24h) [reset = 0h]
INT_EN_CFG0 is shown in Figure 40 and described in Table 22.
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Figure 40. INT_EN_CFG0 Register
23
22
21
20
19
18
17
16
RESERVED
R-0h
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
CRC_CALC_E
N
R/W-0h
6
UV_EN
R/W-0h
5
OV_EN
R/W-0h
4
TW_EN
R/W-0h
3
TSD_EN
R/W-0h
2
SSC_EN
R/W-0h
1
PRTY_FAIL_E
N
R/W-0h
0
SPI_FAIL_EN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 22. INT_EN_CFG0 Register Field Descriptions
Bit
23-8
7
Field
RESERVED
CRC_CALC_EN
6
UV_EN
5
OV_EN
4
TW_EN
3
TSD_EN
2
SSC_EN
1
PRTY_FAIL_EN
0
SPI_FAIL_EN
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
0h
0h
0h
0h
0h
0h
0h
0h
Description
Reserved
0h = INT pin assertion due to CRC calculation completion disabled.
1h = INT pin assertion due to CRC calculation completion enabled.
0h =INT pin assertion due to UV event disabled.
1h = INT pin assertion due to UV event enabled.
0h = INT pin assertion due to OV event disabled.
1h = INT pin assertion due to OV event enabled.
0h = INT pin assertion due to TW event disabled.
1h = INT pin assertion due to TW event enabled.
0h = INT pin assertion due to TSD event disabled.
1h = INT pin assertion due to TSD event enabled.
0h = INT pin assertion due to SSC event disabled.
1h = INT pin assertion due to SSC event enabled.
0h = INT pin assertion due to parity fail event disabled.
1h = INT pin assertion due to parity fail event enabled.
0h = INT pin assertion due to SPI fail event disabled.
1h = INT pin assertion due to SPI fail event enabled.
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