TIC10024-Q1 Datasheet, PDF (39/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

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Bit
Field
6
OV
5
TW
4
TSD
3
SSC
2
PRTY_FAIL
1
SPI_FAIL
TIC10024-Q1
SCPS268 – SEPTEMBER 2017
Table 8. INT_STAT Register Field Descriptions (continued)
Type
RC
RC
Reset
0h
0h
Description
0h = No over-voltage condition occurred or cleared on the V_S pin, or
the event status got cleared after a READ command was executed
on the INT_STAT register.
1h = Over-voltage condition occurred or cleared on the V_S pin.
When the OV bit is flagged to logic 1, it indicates the Over-Voltage
(OV) event has occurred. The bit is also flagged to logic 1 when the
event clears. For more details about the OV operation, please refer
to section VS over-voltage (OV) condition.
0h = No temperature warning event occurred or the event status got
cleared after a READ command was executed on the INT_STAT
register.
1h = Temperature warning event occurred or cleared.
RC
0h
When the TW bit is flagged to logic 1, it indicates the temperature
warning event has occurred. The bit is also flagged to logic 1 when
the event clears. For more details about the temperature warning
operation, please refer to section Temperature Warning (TW)
0h = No temperature Shutdown event occurred or the event status
got cleared after a READ command was executed on the INT_STAT
register.
1h = Temperature Shutdown event occurred or cleared.
RC
0h
When the TSD bit is flagged to logic 1, it indicates the temperature
shutdown event has occurred. The bit is also flagged to logic 1 when
the event clears. For more details about the temperature shutdown
operation, please refer to section Temperature shutdown (TSD)
0h = No switch state change occurred or the status got cleared after
a READ command was executed on the INT_STAT register.
1h = Switch state change occurred.
RC
0h
The Switch State Change (SSC) bit indicates whether input
threshold crossing has occurred from switch inputs IN0 to IN23. This
bit is also flagged to logic 1 after the first polling cycle is completed
after device polling is triggered.
0h = No parity error occurred in the last received SI stream or the
error status got cleared after a READ command was executed on
the INT_STAT register.
1h = Parity error occurred.
RC
0h
When the PRTY_FAIL bit is flagged to logic 1, it indicates the last
SPI Slave In (SI) transaction has a parity error. The device uses odd
parity. If the total number of ones in the received data (including the
parity bit) is an even number, the received data is discarded. The
value of this register bit is mirrored to the PRTY_FLAG SPI status
flag.
0h = 32 clock pulse during a CS = low sequence was detected or the
error status got cleared after a READ command was executed on
the INT_STAT register.
1h = SPI error occurred
When the SPI_FAIL bit is flagged to logic 1, it indicates the last SPI
Slave In (SI) transaction is invalid. To program a complete word, 32
bits of information must be entered into the device. The SPI logic
counts the number of bits clocked into the IC and enables data
latching only if exactly 32 bits have been clocked in. In case the
word length exceeds or does not meet the required length, the
SPI_FAIL bit is flagged to logic 1, and the data received is
considered invalid. The value of this register bit is mirrored to the
SPI_FLAG SPI status flag. Note the SPI_FAIL bit is not flagged if
SCLK is not present.
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