TIC10024-Q1 Datasheet, PDF (23/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

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TIC10024-Q1
SCPS268 – SEPTEMBER 2017
8.3.9.5 Detection Filter
When monitoring the switch input status a detection filter can be configured by setting the DET_FILTER bits in
the CONFIG register to generate Switch Status Change (SSC) interrupt only if the same input status (w.r.t the
threshold) is sampled consecutively. This detection filter can be useful to debounce inputs during a switch toggle
events. Four different filtering schemes are available:
1. Generate an SSC interrupt if the voltage level at an input crossed its threshold
2. Generate an SSC interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t.
the threshold) for at least 2 consecutive polling cycles
3. Generate an SSC interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t.
the threshold) for at least 3 consecutive polling cycles
4. Generate an SSC interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t.
the threshold) for at least 4 consecutive polling cycles
The default value of switch status is stored internally after the 1st detection cycle, even if detection filter (by
configure the DET_FILTER in the CONFIG register) is used. An example is illustrated below with the assumption
that DET_FILTER in register CONFIG is set to 11 (SSC interrupt is generated if the input crosses the threshold
and the status is stable w.r.t. the threshold for at least 4 consecutive detection cycles). Assume switch status
change is detected in the 3rd detection cycle and stays the same for the next 3 cycles.
DETECTION CYCLE
1
2
3
4
5
6
Event
• Default Switch status stored
• INT asserted
—
• SSC flagged
Switch status change
detected
—
— ^{• INT asserted}
• SSC flagged
The detection filter counter is reset to 0 when the TRIGGER bit in the CONFIG register is de-asserted to logic 0.
Upon device reset, the default setting for the detection filter is set to generating an SSC interrupt at every
threshold crossing.
8.3.10 Temperature Monitor
With multiple switch inputs are closed and high wetting current setting is enabled, considerable power could be
dissipated by the device and raise the device temperature. TIC10024-Q1 has integrated temperature monitoring
and protection circuitry to put the device in low power mode to prevent damage due to overheating. Two types of
temperature protection mechanisms are integrated in the device: Temperature Warning (TW) and Temperature
Shutdown (TSD). The triggering temperatures and hysteresis are specified in Table 2 below:
Table 2. Temperature Monitoring Characteristics of TIC10024-Q1
PARAMETER
Temperature warning trigger temperature (T_TW)
Temperature shutdown trigger temperature (T_TSD)
Temperature hysteresis (T_HYS) for T_TW and T_TSD
MIN
TYP
130
140
150
160
15
MAX
155
175
UNIT
°C
°C
°C
8.3.10.1 Temperature Warning (TW)
When the device temperature goes above the temperature warning trigger temperature (T_TW), the TIC10024-Q1
performs the following operations:
1. Generate an interrupt by asserting the INT pin low and flag the TW bit in INT_STAT register to logic 1. The
TEMP bit in the SPI flag is also flagged to logic 1 for all SPI transactions.
2. The TW_STAT bit of the IN_STAT_MISC register is flagged to logic 1.
3. If the TW_CUR_DIS_CSO or TW_CUR_DIS_CSO bit in CONFIG register is set to logic 0 (default), the
wetting current is adjusted down to 2 mA for 10 mA or 15 mA settings. The wetting current stays at its pre-
configured value if 0 mA, 1 mA, 2 mA, or 5 mA setting is used.
4. Maintain the low wetting current as long as the device junction temperature stays above T_TW - T_HYS.
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