TIC10024-Q1 Datasheet, PDF (27/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

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TIC10024-Q1
SCPS268 – SEPTEMBER 2017
Device Functional Modes (continued)
No wetting currents are applied to 0mA- configured inputs, although some biasing current (as specified by
I_{IN_LEAK_0mA}) may still flow in and out of the input. Threshold crossing monitoring is still performed for the input
using the defined threshold(s). The 0mA setting is useful to utilize the integrated comparator to measure applied
voltage on a specific input without being affected by the device wetting current.
8.4.2 Polling Mode
The polling mode can be activated to reduce current drawn in ignition-off condition to conserve battery charge.
Unlike the continuous mode, the current sources/sinks do not stay on continuously in the polling mode. Instead,
they are turned on/off sequentially from IN0 to IN23 and cycled through each individual input channel. The
microcontroller can be put to sleep to reduce overall system power. If a switch status change (SSC) is detected
by the TIC10024-Q1, the INT pin (if enabled for the input channel) is asserted low (and the SSC bit in INT_STAT
register and the SPI status flag SSC are also asserted to logic 1). The INT pin assertion can be used to wake up
the system regulator which, in turn, wakes up the microcontroller as described in section Microcontroller Wake-
Up. The microcontroller can then use SPI communication to read the switch status information.
The polling is activated when the TRIGGER bit in the CONFIG register is set to logic 1.
In polling mode, wetting current is applied to each input for a pre-programmed polling active time between 64 μs
and 2048 μs, set by the POLL_ACT_TIME bits in the CONFIG register . At the end of the wetting current
application, the input voltage is sampled by the comparator. Each input is cycled through in sequential order from
IN0 to IN23. Sampling is repeated at a frequency from 2 ms to 4096 ms, set by the POLL_TIME bits in the
CONFIG register . Wetting currents are applied to closed switches only during the polling active time; hence the
overall system current consumption can be greatly reduced.
Similar to continuous mode, after the first polling cycle, the switch status of each input (below or above detection
threshold) is stored in the register (IN_STAT_COMP) to be used as the default state for subsequent polling
cycles. The INT pin is asserted low to notify the microcontroller that the default switch status is ready to be read.
The SSC bit in INT_STAT register and the SPI status flag SSC are also asserted to logic 1. The INT_STAT
register is cleared and INT pin de-asserted if a SPI READ command is issued to the register. Note the interrupt
is always generated after the 1st polling cycle (after the TRIGGER bit in register CONFIG is set to logic 1). In
subsequent polling cycles the interrupt is generated only if switch status change is detected.
An example of the timing diagram of the polling mode operation is shown in Figure 18.
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