TIC10024-Q1 Datasheet, PDF (15/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

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Feature Description (continued)
VS
Device
OFF
Normal
Operation
Device
OFF
Normal
Operation
TIC10024-Q1
SCPS268 – SEPTEMBER 2017
VPOR_R
VPOR_F
Time
Figure 7. V_S is Lowered Below The POR threshold, Then Ramped Back Up To Complete A POR Cycle
8.3.5.2 Hardware Reset
Microcontroller can toggle the RESET pin to perform a hardware reset to the device. The RESET pin is internally
pulled-down via a resistor (1.25MΩ typical) and must be kept low for normal operation. When the RESET pin is
toggled high, the device enters the reset state with most of the internal blocks turned off and consumes very little
current of I_{S_RESET}. Switch monitoring and SPI communications are stopped in the reset state, and all register
contents are cleared. When RESET pin is toggled back low, all the registers are set to their default values and
the device state machine is re-initialized, similar to a POR event. When the re-initialization process is completed
the INT pin is asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to
notify the microcontroller that the device has completed the reset process.
Note in order to successfully reset the device, the RESET pin needs to be kept high for a minimum duration of
t_RESET. The pin is required to be driven with a stable input (below V_{RESET_L} for logic low or above V_{RESET_H} for
logic H) to prevent the device from accidental reset.
8.3.5.3 Software Reset
In addition to hardware reset the microcontroller can also issue a SPI command to initiate software reset.
Software reset is triggered by setting the RESET bit in the register CONFIG to logic 1, which re-initializes the
device with all registers set to their default values. Once the re-initialization process is completed, the INT pin is
asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to notify the
microcontroller that the device has completed the reset process.
8.3.6 V_S Under-Voltage (UV) Condition
During normal operation of a typical 12V automotive system, the V_S voltage is usually quite stable and stays well
above 11 V. However, the V_S voltage might drop temporarily during certain vehicle operations, such as cold
cranking. If the V_S voltage drops below V_{UV_F}, the TIC10024-Q1 enters the under-voltage (UV) condition since
there is not enough voltage headroom for the device to accurately generate wetting currents. The following
describes the behavior of the TIC10024-Q1 under UV condition:
1. All current sources/sinks de-activate and switch monitoring stops.
2. Interrupt is generated by asserting the INT pin low and the bit UV in the interrupt register (INT_STAT) is
flagged to logic 1. The bit UV_STAT is asserted to logic 1 in the register IN_STAT_MISC. The OI SPI flag is
asserted during any SPI transactions. The INT pin is released and the interrupt register (INT_STAT) is
cleared on the rising edge of CS provided that the interrupt register has been read during the SPI
transaction.
3. SPI communication stays active, and all register settings stay intact without resetting. Previous switch status,
if needed, can be retrieved without interruption.
4. The device continues to monitor the V_S voltage, and the UV condition sustains if the V_S voltage continues to
stay below V_{UV_R}. No further interrupt is generated once cleared.
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