TIC10024-Q1 Datasheet, PDF (34/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

TIC10024-Q1
SCPS268 – SEPTEMBER 2017
www.ti.com
9.2 SPI Sequence
Figure 23 and Figure 24 depict the SPI communication sequence during read and write operations for the
TIC10024-Q1.
... ^{Bit 31}
(MSB)
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 1
Bit 0
(LSB)
SI ^Read/
Write
0
Register address
'RQ¶W FDUH
PAR
... ^{Bit 31}
(MSB)
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 1
Bit 0
(LSB)
SO
Status flag
POR
SPI_
FAIL
PRTY_
FAIL
SSC
RES TEMP
OI
Data out
PAR
Figure 23. TIC10024-Q1 Read SPI Sequence
... ^{Bit 31}
(MSB)
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 1
Bit 0
(LSB)
SI ^Read/
Write
1
Register address
Data in
PAR
... ^{Bit 31}
(MSB)
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 1
Bit 0
(LSB)
SO
Status flag
POR
SPI_
FAIL
PRTY_
FAIL
SSC
RES TEMP
OI
Previous content of the
register addressed
PAR
Figure 24. TIC10024-Q1 Write SPI Sequence
9.2.1 Read Operation
The Read/Write bit (bit 31) of the SI bus needs to be set to logic 0 for a READ operation. The 6-bits address of
the register to be accessed follows next on the SI bus. The content from bit 24 to bit 1 does not represent a valid
command for a read operation and will be ignored. The LSB (bit 0) is the parity bit used to detect communication
errors.
On the SO bus, the status flags will be outputted from the TIC10024-Q1, followed by the data content in the
register that was requested. The LSB is the parity bit used to detect communication errors.
Note there are several test mode registers used in the TIC10024-Q1 in addition to the normal functional
registers, and a READ command to these test registers returns the register content. If a READ command is
issued to an invalid register address, the TIC10024-Q1 returns all 0’s.
9.2.2 Write Operation
The Read/Write bit (bit 31) on the SI bus needs to be set to 1 for a write operation. The 6-bits address of the
register to be accessed follows next on the SI bus. Note the register needs to be a writable configuration register,
or otherwise the command will be ignored. The content from bit 24 to bit 1 represents the data to be written to
the register. The LSB (bit 0) is the parity bit used to detect communication errors.
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