TIC10024-Q1 Datasheet, PDF (35/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

www.ti.com
TIC10024-Q1
SCPS268 – SEPTEMBER 2017
SPI Sequence (continued)
On the SO bus, the status flags will be output from the TIC10024-Q1, followed by the previous data content of
the written register. The previous content of the register is latched after the full register address is decoded in the
SI command (after bit 25 is transmitted). The new data will replace the previous data content at the end of the
SPI transaction if the SI write is a valid command (valid register address and no SPI/parity error). If the write
command is invalid, the new data will be ignored and the register content will remain unchanged. The LSB is the
parity bit used to detect communication errors.
Note there are several test mode registers used in the TIC10024-Q1 in addition to the normal functional
registers. A WRITE command to these test registers has no effect on the register content, even though the
register content is returned on the SO output. If a WRITE command is issued to an invalid register address, the
SO output returns all 0’s.
9.2.3 Status Flag
The status flags are output from SO during every READ or WRITE SPI transaction to indicate system conditions.
These bits do not belong to an actual register, but their content is mirrored from the interrupt register INT_STAT.
A READ command executed on the INT_STAT would clear both the bits inside the register and the status flag.
The following table describes the information that can be obtained from each SPI status flag:
SYMBOL
POR
SPI_FAIL
PRTY_FAIL
SSC
RES
TEMP
OI
Table 4. TIC10024-Q1 SPI Status Flag Description
NAME
DESCRIPTION
Power-on Reset
SPI Error
Parity Fail
Switch State Change
Reserved
Temperature Event
Other Interrupt
This flag mirrors the POR bit in the interrupt register INT_STAT, and it indicates, if set to 1, that a
reset event has occurred. This bit is asserted after a successful power-on-reset, hardware reset, or
software reset. Refer to section Device Reset for more details.
This flag mirrors the SPI_FAIL bit in the interrupt register INT_STAT and it indicates, if set to 1, that the last SPI
Slave In (SI) transaction is invalid. To program a complete word, 32 bits of information must be entered into the
device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly 32
bits have been clocked in. In case the word length exceeds or does not meet the required size, the SPI_FAIL bit,
which mirrors its value to this SPI_FAIL status flag, of the interrupt register INT_STAT will be set to 1 and the
INT pin will be asserted low. The data received will be considered invalid. Once the INT_STAT register is read,
its content will be cleared on the rising edge of CS. The SPI_FAIL status flag, which mirrors the SPI_FAIL bit in
the INT_STAT register, will also be de-asserted. Note the SPI_FAIL bit is not flagged if SCLK is not present.
This flag mirrors the PRTY_FAIL bit in the interrupt register INT_STAT and it indicates, if set to 1, that the last
SPI Slave In (SI) transaction has a parity error. The device uses odd parity. If the total number of ones in the
received data (including the parity bit) is an even number, the received data is discarded. The INT will be
asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1, and the
PRTY_FAIL status flag, which mirrors the PRTY_FAIL bit in the INT_STAT register, is also set to 1. Once the
INT_STAT register is read, its content will be cleared on the rising edge of CS. The PRTY_FAIL status flag,
which mirrors the PRTY_FAIL bit in the INT_STAT register, will also be de-asserted.
This flag mirrors the SSC bit in the interrupt register INT_STAT and it indicates, if set to 1, that one or more
switch inputs crossed a threshold. To determine the origin of the state change, the microcontroller can read the
content of the register IN_STAT_COMP. Once the interrupt register (INT_STAT) is read, its content will be
cleared on the rising edge of CS. The SSC status flag, which mirrors the SSC bit in the INT_STAT register, will
also be de-asserted.
This flag is reserved and is always at logic 0.
This flag is set to 1 if either Temperature Warning (TW) or Temperature Shutdown (TSD) bit in the interrupt
register INT_STAT is flagged to 1. It indicates a TW event or a TSD event has occurred. It is also flagged to 1 if
a TW event or a TSD event is cleared. The interrupt register INT_STAT should be read to determine which event
occurred. The SPI master can also read the IN_STAT_MISC register to get information on the temperature
status of the device. Once the interrupt register (INT_STAT) is read, its content will be cleared on the rising edge
of CS, and the TEMP status flag will also be de-asserted.
Other interrupt include interrupts such as OV, UV, CRC_CALC and CHK_FAIL. This flag will be asserted 1 when
any of the abovementioned bits is flagged in the interrupt register INT_STAT. The interrupt register INT_STAT
should be read to determine which event(s) occurred. The SPI master can also read the IN_STAT_MISC register
to get information on the latest status of the device. Once the INT_STAT register is read, its content will be
cleared on the rising edge of CS, and the OI status flag will also be de-asserted.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TIC10024-Q1
Submit Documentation Feedback
35