TIC10024-Q1 Datasheet, PDF (38/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

TIC10024-Q1
SCPS268 – SEPTEMBER 2017
www.ti.com
9.4.2 INT_STAT Register (Offset = 2h) [reset = 1h]
INT_STAT is shown in Figure 26 and described in Table 8.
Return to Summary Table.
This register records the information of the event as it occurs in the device. A READ command executed on this
register clears its content and resets the register to its default value. The INT pin is released at the rising edge of
the CS pin from the READ command.
Figure 26. INT_STAT Register
23
22
21
20
19
18
17
16
RESERVED
R-0h
15
14
13
12
RESERVED
CHK_FAIL
R-0h
RC-0h
11
10
RESERVED
R-0h
9
8
CRC_CALC
RC-0h
7
UV
RC-0h
6
OV
RC-0h
5
TW
RC-0h
4
TSD
RC-0h
3
SSC
RC-0h
2
PRTY_FAIL
RC-0h
1
SPI_FAIL
RC-0h
0
POR
RC-1h
LEGEND: R = Read only; RC = Read to clear
Table 8. INT_STAT Register Field Descriptions
Bit
23-14
13
Field
RESERVED
CHK_FAIL
Type
R
RC
Reset
0h
0h
Description
RESERVED
0h = Default factory setting is successfully loaded upon device
initialization or the event status got cleared after a READ command
was executed on the INT_STAT register.
1h = An error is detected when loading factory settings into the
device upon device initialization.
12-9
8
RESERVED
CRC_CALC
R
0h
RC
0h
During device initialization, factory settings are programmed into the
device to allow proper device operation. The device performs a self-
check after the device is programmed to diagnose whether correct
settings are loaded. If the self-check returns an error, the CHK_FAIL
bit is flagged to logic 1 along with the POR bit. The host controller is
then recommended to initiate a software reset (see section Software
Reset) to re-initialize the device and allow correct settings to be re-
programmed.
RESERVED
0h = CRC calculation is running, not started, or was acknowledged
after a READ command was executed on the INT_STAT register.
1h = CRC calculation is finished.
7
UV
RC
0h
CRC calculation (see section Cyclic Redundancy Check (CRC)) can
be triggered to make sure correct register values are programmed
into the device. Once the calculation is completed, the CRC_CALC
bit is flagged to logic 1 to indicate completion of the calculation, and
the result can then be accessed from the CRC (offset = 3h) register.
0h = No under-voltage condition occurred or cleared on the V_S pin,
or the event status got cleared after a READ command was
executed on the INT_STAT register.
1h = Under-voltage condition occurred or cleared on the V_S pin.
When the UV bit is flagged to logic 1, it indicates the Under-Voltage
(UV) event has occurred. The bit is also flagged to logic 1 when the
event clears. For more details about the UV operation, please refer
to section VS under-voltage (UV) condition.
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