TIC10024-Q1 Datasheet, PDF (33/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

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TIC10024-Q1
SCPS268 – SEPTEMBER 2017
9 Programming
The SPI interface communication consists of the 4 pins: CS, SCLK, SI, and SO. The interface can work with
SCLK frequency up to 4 MHz.
9.1 SPI Communication Interface Buses
9.1.1 Chip Select (CS)
The system microcontroller selects the TIC10024-Q1 to receive communication using the CS pin. With the CS
pin in a logic LOW state, command words may be sent to the TIC10024-Q1 via the serial input (SI) pin, and the
device information can be retrieved by the microcontroller via the serial output (SO) pin. The falling edge of the
CS enables the SO output and latches the content of the interrupt register INT_STAT. The microcontroller may
issue a READ command to retrieve information stored in the registers. Rising edge on the CS pin initiates the
following operations:
1. Disable the output driver and makes SO high-impedance.
2. INT pin is reset to logic HIGH if a READ command to the INT_STAT register was issued during CS = LOW.
To avoid corrupted data, it is essential the HIGH-to-LOW and LOW-to-HIGH transitions of the CS signal occur
only when SCLK is in a logic LOW state. A clean CS signal is needed to ensure no incomplete SPI words are
sent to the device. The CS pin should be externally pulled up to VDD by a 10 kΩ resistor.
9.1.2 System Clock (SCLK)
The system clock (SCLK) input is used to clock the internal shift register of the TIC10024-Q1. The SI data is
latched into the input shift register on the falling edge of the SCLK signal. The SO pin shifts the device stored
information out on the rising edge of SCLK. The SO data is available for the microcontroller to read on the falling
edge of SCLK.
False clocking of the shift register must be avoided to ensure validity of data and it is essential the SCLK pin be
in a logic LOW state whenever CS makes any transition. Therefore, it is recommended that the SCLK pin gets
pulled to a logic LOW state as long as the device is not accessed and CS is in a logic HIGH state. When the CS
is in a logic HIGH state, any signal on the SCLK and SI pins will be ignored and the SO pin remains as a high
impedance output. Refer to Figure 23 and Figure 24 for examples of typical SPI read and write sequence.
9.1.3 Slave In (SI)
The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling
edge of the SCLK. To program a complete word, 32 bits of information must be entered into the device. The SPI
logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been
clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit of the
INT_STAT register is asserted to logic 1 and the INT pin will be asserted low. The data received is considered
invalid. Note the SPI_FAIL bit is not flagged if SCLK is not present.
9.1.4 Slave Out (SO)
The SO pin is the output from the internal shift register. The SO pin remains high-impedance until the CS pin
transitions to a logic LOW state. The negative transition of CS enables the SO output driver and drives the SO
output to the HIGH state (by default). The first positive transition of SCLK makes the status data bit 31 available
on the SO pin. Each successive positive clock makes the next status data bit available for the microcontroller to
read on the falling edge of SCLK. The SI/SO shifting of the data follows a first-in, first-out scheme, with both
input and output words transferring the most significant bit (MSB) first.
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