TIC10024-Q1 Datasheet, PDF (6/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

TIC10024-Q1
SCPS268 – SEPTEMBER 2017
www.ti.com
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
TIC10024-Q1
DCP (TSSOP)
UNIT
38 PINS
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
33.6
°C/W
18.4
°C/W
15.2
°C/W
0.5
°C/W
15.0
°C/W
1.2
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, V_S = 4.5 V to 35 V, and V_DD = 3 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
POWER SUPPLY
I_{S_CONT}
Continuous mode V_S Continuous mode, I_WETT= 10 mA, all switches open, no active
power supply current comparator operation, no unserviced interrupt
5.6
7
I_{S_POLL_COMP_25}
I_{S_POLL_COMP_85}
I_{S_POLL_COMP}
I_{S_RESET}
Polling mode V_S
power supply
average current
Reset mode V_S
power supply current
T_A= 25°
T_A= -40° to 85°C
T_A= -40° to 125°C
Polling mode, t_POLL= 64 ms, t_POLL_ACT= 128
µs, all switches open, I_WETT= 10 mA, no
unserviced interrupt
Reset mode, V_RESET= V_DD. V_S= 12 V, all switches open, T_A=25°C
68
100
68
110
68
170
12
17
I_{S_IDLE_25}
I_{S_IDLE_85}
I_{S_IDLE}
V_S power supply
average current in
idle state
TRIGGER bit in CONFIG register = logic 0, T_A= 25°C, no
unserviced interrupt
TRIGGER bit in CONFIG register = logic 0, T_A= -40°C to 85°C, no
unserviced interrupt
TRIGGER bit in CONFIG register = logic 0, T_A= -40°C to 125°C,
no unserviced interrupt
50
75
50
95
50
145
I_DD
V_{POR_R}
V_{POR_F}
Logic supply current
from V_DD
SCLK = SI = 0 V, CS = INT = V_DD, no SPI communication
1.5
10
Power on reset
Threshold for rising V_S from device OFF condition resulting in INT
pin assertion and a flagged POR bit in the INT_STAT register
3.85
4.5
(POR) voltage for V_{S Threshold for falling VS from device normal operation to reset}
mode and loss of SPI communication
1.95
2.8
V_{OV_R}
Over-voltage (OV)
condition for V_S
Threshold for rising V_S from device normal operation resulting in
INT pin assertion and a flagged OV bit in the INT_STAT register
35
40
V_{OV_HYST}
Over-voltage (OV)
condition hysteresis
for V_S
1
3.5
V_{UV_R}
V_{UV_F}
Under-voltage (UV)
Threshold for rising V_S from under-voltage condition resulting in
INT pin assertion and a flagged UV bit in the INT_STAT register
3.85
4.5
condition for V_S
Threshold for falling V_S from under-votlage condition resulting in
INT pin assertion and a flagged UV bit in the INT_STAT register
3.7
4.4
V_{UV_HYST}
Under-voltage (UV)
condition hysteresis
for V_S(1)
75
275
V_{DD_F}
Threshold for falling V_DD resulting in loss of SPI communication
2.5
2.9
V_{DD_HYST}
Valid V_DD voltage
hysteresis
50
150
(1) Specified by design.
UNIT
mA
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
mV
V
mV
6
Submit Documentation Feedback
Product Folder Links: TIC10024-Q1
Copyright © 2017, Texas Instruments Incorporated