TIC10024-Q1 Datasheet, PDF (26/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

TIC10024-Q1
SCPS268 – SEPTEMBER 2017
www.ti.com
8.4 Device Functional Modes
The TIC10024-Q1 has 2 modes of operation: continuous mode and polling mode. The following sections
describe the two operation modes in details as well as some of the advanced features that could be activated
during normal operations.
8.4.1 Continuous Mode
In continuous mode, wetting current is continuously applied to each enabled input channel, and the status of
each channel is sampled sequentially (starting from the IN0 to IN23). The TIC10024-Q1 monitors enabled inputs
and issues an interrupt (if enabled) if a switch status change event is detected. The wetting current setting for
each input can be individually adjusted by configuring the WC_CFG0 and WC_CFG1 to the 0mA, 1mA, 2mA,
5mA, 10mA, or 15mA setting.
Figure 17 below illustrates an example of the timing diagram of the detection sequence in continuous mode. After
the TRIGGER bit in register CONFIG is set to logic 1, it takes t_STARTUP to activate the wetting current for all
enabled inputs. The wetting currents stay on continuously, while each input is routed to the comparator for
sampling in a sequential fashion. After detection is done for an input, the switch status (below or above detection
threshold) is stored in the register (IN_STAT_COMP) to be used as the default state for subsequent detection
cycles. After the end of the first polling cycle, the INT pin is asserted low to notify the microcontroller that the
default switch status is ready to be read. The SSC bit in INT_STAT register and the SPI status flag SSC are also
asserted to logic 1. The polling cycle time (t_POLL) determines how frequently each input is sampled and can be
configured in the register CONFIG.
Wetting
current
TRIGGER bit set
to logic 1 in
CONFIG register
ttPOLL_TIMEt
Input sampling restarts
from first enabled input
after tPOLL_TIME
ttSTARTUPt
IN0
tCOMPt
IN1
tCOMPt
IN3
IN23
/INT
x Default input status is stored
x /INT pin is asserted after the
1^st detection cycle
Time
Figure 17. An Example Of The Detection Sequence In Continuous Mode
The INT_STAT register is cleared and INT pin de-asserted if a SPI READ command is issued to the register.
Note the interrupt is always generated after the 1st detection cycle (after the TRIGGER bit in register CONFIG is
set to logic 1). In subsequent detection cycles, the interrupt is generated only if switch status change is detected.
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