TIC10024-Q1 Datasheet, PDF (19/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

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TIC10024-Q1
SCPS268 – SEPTEMBER 2017
8.3.9 Interrupt Generation and INT Assertion
The INT pin is an active-low, open-drain output that asserts low when an event (switch input state change,
temperature warning, over-voltage shutdown…etc) is detected by the TIC10024-Q1. An external pull-up resistor
to V_DD is needed on the INT pin (see Figure 10). The INT pin can also be connected directly to a 12-V
automotive battery to support the microcontroller wake-up feature, as describe in section Microcontroller Wake-
Up.
TIC10024-Q1
Microcontroller
VDD
VDD
/INT
GPI
AGND
AGND
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 10. INT Connection Example #1
8.3.9.1 INT Pin Assertion Scheme
TIC10024-Q1 supports two configurable schemes for INT assertion: static and dynamic. The scheme can be
adjusted by configuring the INT_CONFIG bit in the CONFIG register.
If the static INT assertion scheme is used (INT_CONFIG = 0 in the CONFIG register), the INT pin is asserted low
upon occurrence of an event. The INT pin is released on the rising edge of CS only if a READ command has
been issued to read the INT_STAT register while CS is low, otherwise the INT will be kept low indefinitely. The
content of the INT_STAT interrupt register is latched on the first rising edge of SCLK after CS goes low for every
SPI transaction, and the content is cleared upon a READ command issued to the INT_STAT register, as
illustrated in Figure 11.
Event occurance
x INT_STAT register
content cleared
x /INT pin released
/INT
/CS
Register READ
Register READ
(non- INT_STAT register) (INT_STAT register)
Figure 11. Static INT Assertion Scheme
In some system implementations an edge-triggered based microcontroller might potentially miss the INT
assertion if it is configured to the static scheme, especially when the microcontroller is in the process of waking
up. To prevent missed INT assertion and improve robustness of the interrupt behavior, the TIC10024-Q1
provides the option to use the dynamic assertion scheme for the INT pin. When the dynamic scheme is used
(INT_CONFIG= 1 in the CONFIG register), the INT pin is asserted low for a duration of t_{INT_ACTIVE} and is de-
asserted back to high if the INT_STAT register has not been read after t_{INT_ACTIVE} has elapsed. The INT is kept
high for a duration of t_{INT_INACTIVE}, and is re-asserted low after t_{INT_INACTIVE} has elapsed. The INT pin continues to
toggle until the INT_STAT register is read.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TIC10024-Q1
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