TIC10024-Q1 Datasheet, PDF (20/81 Pages) Texas Instruments – 24-Input Multiple Switch Detection Interface (MSDI) Device With Adjustable Wetting Current for Automotive Systems

TIC10024-Q1
SCPS268 – SEPTEMBER 2017
www.ti.com
If the INT_STAT register is read when INT pin is asserted low, the INT pin is released on the READ command’s
CS rising edge and the content of the INT_STAT register is also cleared, as shown in Figure 12. If the INT_STAT
register is read when INT pin is de-asserted, the content of the INT_STAT register is cleared on the READ
command’s CS rising edge, and the INT pin is not re-asserted back low, as shown in Figure 13.
Event
occurance
ttINT_INACTIVEt
x INT_STAT register
content cleared
x /INT pin released
/INT
tINT_ACTIVE
/CS
Register READ
(INT_STAT register)
Figure 12. Dynamic INT Assertion Scheme With INT_STAT Register Read During t_{INT_ACTIVE}
Event
occurance
/INT
/CS
ttINT_INACTIVEt
tINT_ACTIVE
x INT_STAT register
content cleared
x /INT pin will not be re-
asserted tINT_INACTIVE
after /INT returns high
Register READ
(INT_STAT register)
Figure 13. Dynamic INT Assertion Scheme With INT_STAT Register Read During t_{INT_INACTIVE}
The static INT assertion scheme is selected by default upon device reset. The INT pin assertion scheme can
only be changed when bit TRIGGER is logic 0 in the CONFIG register.
8.3.9.2 Interrupt Idle Time (t_{INT_IDLE}) Time
Interrupt idle time (t_{INT_IDLE}) is implemented in TIC10024-Q1 to:
• Allow the INT pin enough time to be pulled back high by the external pull-up resistor and allow the next
assertion to be detectable by an edge-triggered microcontroller.
• Minimize the chance of glitching on the INT pin if back-to-back events occur.
When there is a pending interrupt event and the interrupt event is not masked, t_{INT_IDLE} is applied after the READ
command is issued to the INT_STAT register. If another event occurs during the interrupt idle time the INT_STAT
register content is updated instantly but the INT pin is not asserted low until t_{INT_IDLE} has elapsed. If another
READ command is issued to the INT_STAT register during t_{INT_IDLE}, the INT_STAT register content is cleared
immediately, but the INT pin is not re-asserted back low after t_{INT_IDLE} has elapsed. An example of the interrupt
idle time is given below to illustrate the INT pin behavior under the static INT assertion schemes:
20
Submit Documentation Feedback
Product Folder Links: TIC10024-Q1
Copyright © 2017, Texas Instruments Incorporated