DS90UR124-Q1 Datasheet, PDF (6/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
www.ti.com
Pin Functions: PAG Package (continued)
PIN
I/O
NO.
NAME
DESCRIPTION
50
RES0
LVCMOS_I Reserved. This pin MUST be tied LOW.
1-6,
17,
18,
33, 34
RES0
NC
No Connection. Pins are not physically connected to the die. Recommendation is to leave pin
open or tie it to LOW.
Receiver Power Down Bar
48
RPWDNB
LVCMOS_I
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), R_OUT[23-0], RCLK, and LOCK are in Tri-
state standby mode, PLL is shutdown to minimize power consumption.
Receiver Clock Edge Select Pin
55
RRFB
LVCMOS_I RRFB = H; R_OUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; R_OUT LVCMOS Outputs strobed on the Falling Clock Edge.
LVCMOS Output Slew Rate Control
64
SLEW
LVCMOS_I SLEW = L; Low drive output at 2 mA (default)
SLEW = H; High drive output at 4 mA
BIST MODE PINS (See Application and Implementation for more details.)
Control Pin for BIST Mode Enable
61
BISTEN
LVCMOS_I
BISTEN = L; Default at Low, Normal Mode.
BISTEN = H; BIST mode active. When BISTEN = H and DS90UR241 DIN[23:0] = Low or
Floating; device will go to BIST mode accordingly. Check PASS output pin for test status.
BIST Mode selection. Control pin for which Deserializer is set for BIST reporting mode.
62
BISTM
LVCMOS_I BISTM = L; Default at Low, Status of all R_OUT with respective bit error on cycle-by-cycle basis
BISTM = H; Total accumulated bit error count provided on ROUT[7:0] (binary counter up to 255)
Pass flag output for @Speed BIST Test operation.
45
PASS
LVCMOS_O PASS = L; BIST failure
PASS = H; LOCK = H before BIST can be enabled, then 1x10^-9 error rate achieved across link.
LVDS SERIAL INTERFACE PINS
53
R_IN+
LVDS_I
54
R_IN−
LVDS_I
POWER / GROUND PINS
Receiver LVDS True (+) Input — This input is intended to be terminated with a 100Ω load to the
R_IN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
Receiver LVDS Inverted (−) Input — This input is intended to be terminated with a 100Ω load to
the R_IN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
51
VDD
VDD
Analog LVDS Voltage Supply, POWER
59
VDD
VDD
Analog Voltage Supply, PLL POWER
57
VDD
VDD
Analog Voltage supply, PLL VCO POWER
32
VDD
VDD
Digital Voltage Supply, LOGIC POWER
46
VDD
VDD
Digital Voltage Supply, LOGIC POWER
40
VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
26
VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
11
VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
52
VSS
GND
Analog LVDS GROUND
58
VSS
GND
Analog Ground, PLL GROUND
56
VSS
GND
Analog Ground, PLL VCO GROUND
31
VSS
GND
Digital Ground, Logic GROUND
47
VSS
GND
Digital Ground, LOGIC GROUND
39
VSS
GND
Digital Ground, LVCMOS Output GROUND
25
VSS
GND
Digital Ground, LVCMOS Output GROUND
12
VSS
GND
Digital Ground, LVCMOS Output GROUND
6
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