DS90UR124-Q1 Datasheet, PDF (11/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Deserializer Switching Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS PIN/FREQ.
MIN
t_ROS
t_ROH
t_ROS
t_ROH
R_OUT (8:15) Setup Data to RCLK
(Group 2)
R_OUT (8:15) Hold Data to RCLK
(Group 2)
R_OUT (16:23) Setup Data to RCLK
(Group 3)
R_OUT (16:23) Setup Data to RCLK
(Group 3)
PTOSEL = L,
SLEW = H,
Figure 18
R_OUT [8:15],
LOCK
R_OUT [16:23]
(0.35)× t_RCP
(0.35)× t_RCP
(0.35)× t_RCP
(0.35)× t_RCP
t_ROS
t_ROH
R_OUT (0:7) Setup Data to RCLK
(Group 1)
R_OUT (0:7) Hold Data to RCLK
(Group 1)
R_OUT[0:7]
(0.35)× t_RCP
(0.35)× t_RCP
t_ROS
t_ROH
R_OUT (8:15) Setup Data to RCLK
(Group 2)
R_OUT (8:15) Hold Data to RCLK
(Group 2)
PTOSEL = H,
SLEW = H,
Figure 17
R_OUT [8:15],
LOCK
(0.35)× t_RCP
(0.35)× t_RCP
t_ROS
t_ROH
R_OUT (16:23) Setup Data to RCLK
(Group 3)
R_OUT (16:23) Setup Data to RCLK
(Group 3)
R_OUT [16:23]
(0.35)× t_RCP
(0.35)× t_RCP
t_HZR
HIGH to Tri-state Delay
t_LZR
LOW to Tri-state Delay
t_ZHR
Tri-state to HIGH Delay
t_ZLR
Tri-state to LOW Delay
t_DD
Deserializer Delay
PTOSEL = H,
Figure 16
PTOSEL = H,
Figure 14
R_OUT [0:23],
RCLK, LOCK
RCLK
t_DSR
Deserializer PLL Lock Time from
Powerdown
See Figure 16
5 MHz
43 MHz
RxIN_T
OL-L
Receiver INput TOLerance Left
See
Figure 19
5 MHz–43 MHz
RxIN_T
OL-R
Receiver INput TOLerance Right
See
Figure 19
5 MHz–43 MHz
TYP
(0.5×t_RCP)–
3 UI
(0.5×t_RCP)–
3 UI
(0.5×t_RCP)–
3 UI
(0.5×t_RCP)–
3 UI
(0.5×t_RCP)–
2 UI
(0.5×t_RCP)+
2 UI
(0.5×t_RCP)−
1 UI
(0.5×t_RCP)+
1 UI
(0.5×t_RCP)+
1 UI
(0.5×t_RCP)–
1 UI
3
3
3
3
[5+(5/56)]T
+3.7
MAX
10
10
10
10
[5+(5/56)]T
+8
128k*T
128k*T
0.25
0.25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
UI
UI
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
Figure 3. Serializer Input Checkerboard Pattern
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