DS90UR124-Q1 Datasheet, PDF (10/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
7.6 Serializer Input Timing Requirements for TCLK
over recommended operating supply and temperature ranges unless otherwise specified
MIN
t_TCP
t_TCIH
t_TCIL
t_CLKT
t_JIT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
Figure 7
Figure 6
f = 43 MHz
f = 33 MHz
23.25
0.3 T
0.3 T
7.7 Serializer Switching Characteristics
over recommended operating supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
t_LLHT
t_LHLT
t_DIS
t_DIH
t_HZD
t_LZD
t_ZHD
t_ZLD
t_PLD
t_SD
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
D_IN (0:23) Setup to TCLK
D_IN (0:23) Hold from TCLK
D_OUT ± HIGH to Tri-state Delay
D_OUT ± LOW to Tri-state Delay
D_OUT ± Tri-state to HIGH Delay
D_OUT ± Tri-state to LOW Delay
Serializer PLL Lock Time
Serializer Delay
R_L = 100 Ω, VODSEL = L,
C_L = 10 pF to GND, Figure 5
R_L = 100 Ω, C_L = 10 pF to GND
Figure 7
R_L = 100 Ω,
C_L = 10 pF to GND
Figure 8
R_L = 100 Ω
R_L = 100 Ω, PRE = OFF,
RAOFF = L, TRFB = H,
Figure 10
R_L = 100 Ω, PRE = OFF,
RAOFF = L, TRFB = L,
Figure 10
4
4
3.5T+2
3.5T+2
5 MHz–43 MHz,
TxOUT TxOUT_Eye_Opening.
_E_O TxOUT_E_O centered on (tBIT/)2
R_L = 100 Ω, C_L = 10 pF to GND,
RANDOM pattern
0.76
Figure 11
www.ti.com
NOM
T
0.5 T
0.5 T
2.5
MAX
200
0.7 T
0.7 T
±100
±130
UNIT
ns
ns
ns
ns
ps
TYP
MAX UNIT
245
550 ps
264
550 ps
ns
ns
10
15 ns
10
15 ns
75
150 ns
75
150 ns
10 ms
3.5T+10
ns
3.5T+10
0.84
UI
7.8 Deserializer Switching Characteristics
over recommended operating supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS PIN/FREQ.
MIN
TYP
t_RCP
Receiver out Clock Period
t_RDC
RCLK Duty Cycle
t_RCP = t_TCP,
PTOSEL = H
PTOSEL = H,
SLEW = L
RCLK
Figure 17
23.25
45%
T
50%
t_CLH
LVCMOS Low-to-High Transition
Time
C_L = 4 pF
(lumped load),
t_CHL
LVCMOS High-to-Low Transition
Time
SLEW = H
R_OUT [0:23],
RCLK, LOCK
1.5
1.5
t_CLH
LVCMOS Low-to-High Transition
Time
C_L = 4 pF
(lumped load),
t_CHL
LVCMOS High-to-Low Transition
Time
SLEW = L
R_OUT [0:23],
RCLK, LOCK
2.0
2.0
t_ROS
t_ROH
R_OUT (0:7) Setup Data to RCLK
(Group 1)
R_OUT (0:7) Hold Data to RCLK
(Group 1)
PTOSEL = L,
SLEW = H,
Figure 18
R_OUT[0:7]
(0.35)× t_RCP
(0.35)× t_RCP
(0.5×t_RCP)–
3 UI
(0.5×t_RCP)–
3 UI
MAX UNIT
200 ns
55%
2.5 ns
2.5 ns
3.5 ns
3.5 ns
ns
ns
10
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: DS90UR124-Q1 DS90UR241-Q1