DS90UR124-Q1 Datasheet, PDF (15/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

www.ti.com
DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
R_IN0-23
DCA, DCB
RCLK
START
STOP START
STOP START
STOP START
STOP
BIT _{SYMBOL N} BIT BIT _{SYMBOL N+1} BIT BIT _{SYMBOL N+2} BIT BIT _{SYMBOL N+3} BIT
012
23
012
23
012
23
012
23
t_DD
R_OUT0-23
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
Figure 14. Deserializer Delay
SYMBOL N
REN
500:
V_REF
C_L = 8 pF
+
-
V_REF = V_DD/2 for t_ZLR or t_LZR,
V_REF = 0V for t_ZHR or t_HZR
NOTE:
C_L includes instrumentation and fixture capacitance within 6 cm of R_OUT [23:0].
VOH
REN
VOL
V_DD/2
t_LZR
V_DD/2
t_ZLR
VOL
R_OUT [23:0]
VOH
t_HZR
VOL + 0.5V
t_ZHR
VOL + 0.5V
VOH - 0.5V
VOH + 0.5V
Figure 15. Deserializer Tri-State Test Circuit and Timing
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: DS90UR124-Q1 DS90UR241-Q1