DS90UR124-Q1 Datasheet, PDF (16/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
2.0V
PWDN
R_IN±
t_DSR
LOCK TRI-STATE
R_OUT [0:23]
RCLK
TRI-STATE
TRI-STATE
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0.8V
}v[šŒ
TRI-STATE
t_HZR or t_LZR
TRI-STATE
TRI-STATE
REN
Figure 16. Deserializer PLL Lock Times and RPWDNB Tri-State Delay
t_RCP
RCLK
V_DD/2
t_RDC
t_RDC
V_DD/2
t_ROS
t_ROH
R_OUT [7:0]
(group 1)
V_DD/2
| -2 UI
Data Valid
Before RCLK
Data Valid
After RCLK
t_ROS
t_ROH
V_DD/2
| +2 UI
R_OUT [15:8]
(group 2)
V_DD/2
Data Valid
Before RCLK
Data Valid
After RCLK
V_DD/2
| -1 UI
t_ROS
t_ROH
| +1 UI
R_OUT [23:16]
(group 3)
V_DD/2
Data Valid
Before RCLK
Data Valid
After RCLK
V_DD/2
| +1 UI
| -1 UI
Figure 17. Deserializer Setup and Hold Times and PTO, PTOSEL = H
16
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