DS90UR124-Q1 Datasheet, PDF (1/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
DS90URxxx-Q1 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and
Deserializer Chipset
1 Features
•1 Supports Displays With 18-Bit Color Depth
• 5-MHz to 43-MHz Pixel Clock
• Automotive-Grade Product AEC-Q100 Grade 2
Qualified
• 24:1 Interface Compression
• Embedded Clock With DC Balancing Supports
AC-Coupled Data Transmission
• Capable to Drive up to 10 Meters Shielded
Twisted-Pair Cable
• No Reference Clock Required (Deserializer)
• Meets ISO 10605 ESD – Greater than 8 kV HBM
ESD Structure
• Hot Plug Support
• EMI Reduction – Serializer Accepts Spread
Spectrum Input; Data Randomization and
Shuffling on Serial Link; Deserializer Provides
Adjustable PTO (Progressive Turnon) LVCMOS
Outputs
• @Speed BIST (Built-In Self-Test) to Validate
LVDS Transmission Path
• Individual Power-Down Controls for Both
Transmitter and Receiver
• Power Supply Range 3.3 V ±10%
• 48-Pin TQFP Package for Transmitter and 64-Pin
TQFP Package for Receiver
• Temperature Range: –40°C to 105°C
• Backward-Compatible Mode With
DS90C241/DS90C124
Applications Diagram
Host
(Graphics/Video Processor, ECU)
Display
(Infotainment, Instrument Cluster, CID)
DE
RGB Data
Video
Source _Clock
HSYNC
DS90UR241
Serializer
VSYNC
(LVCMOS)
FPD-Link II
1 Pair
(LVDS)
DE
RGB Data
DS90UR124
Deserializer ^Clock
HSYNC
VSYNC
(LVCMOS)
LCD
2 Applications
• Automotive Central Information Displays
• Automotive Instrument Cluster Displays
• Automotive Heads-Up Displays
• Remote Camera-Based Driver Assistance
Systems
3 Description
The DS90URxxx-Q1 chipset translates a 24-bit
parallel bus into a fully transparent data/control FPD-
Link II LVDS serial stream with embedded clock
information. This chipset is ideally suited for driving
graphical data to displays requiring 18-bit color depth:
RGB666 + HS, VS, DE + three additional general-
purpose data channels. This single serial stream
simplifies transferring a 24-bit bus over PCB traces
and cable by eliminating the skew problems between
parallel data and clock paths. The device saves
system cost by narrowing data paths that in turn
reduce PCB layers, cable width, and connector size
and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS
signaling on the high-speed I/O. FPD-Link II LVDS
provides a low-power and low-noise environment for
reliably transferring data over a serial transmission
path. By optimizing the Serializer output edge rate for
the operating frequency range, EMI is further
reduced.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UR124-Q1
TQFP (64)
10.00 mm × 10.00 mm
DS90UR241-Q1
TQFP (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
VODSEL
PRE
DEN
RAOFF
REN
24
DIN
TRFB
DOUT+
DOUT-
RIN+
RIN-
24
ROUT
TCLK
PLL
TPWDNB
Timing
and
Control
SERIALIZER ± DS90UR241
RAOFF
RRFB
RPWDNB
BISTEN
BISTM
SLEW
PTOSEL
PLL
Timing
and
Control
LOCK
Clock
Recovery
DESERIALIZER ± DS90UR124
RCLK
PASS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.