DS90UR124-Q1 Datasheet, PDF (21/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Feature Description (continued)
8.3.7 AC-Coupling and Termination
The DS90UR241 and DS90UR124 supports AC-coupled interconnects through integrated DC balanced
encoding/decoding scheme. To use the Serializer and Deserializer in an AC-coupled application, insert external
AC-coupling capacitors in series in the LVDS signal path as illustrated in Figure 29. The Deserializer input stage
is designed for AC-coupling by providing a built-in AC bias network which sets the internal V_CM to +1.8V. With AC
signal coupling, capacitors provide the AC-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest available package should be used for the AC-coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The most common
used capacitor value for the interface is a 100 nF (0.1 uF). NPO class 1 or X7R class 2 type capacitors are
recommended. 50 WVDC should be the minimum used for the best system-level ESD performance.
A termination resistor across DOUT± and RIN± is also required for proper operation to be obtained. The
termination resistor should be equal to the differential impedance of the media being driven. This should be in the
range of 90 to 132 Ω. 100 Ω is a typical value common used with standard 100-Ω transmission media. This
resistor is required for control of reflections and also completes the current loop. It should be placed as close to
the Serializer DOUT± outputs and Deserializer RIN± inputs to minimize the stub length from the pins. To match
with the deferential impedance on the transmission line, the LVDS I/O are terminated with 100-Ω resistors on
Serializer DOUT± outputs pins and Deserializer RIN± input pins.
8.3.7.1 Receiver Termination Option 1
A single 100-Ω termination resistor is placed across the RIN± pins (see Figure 29). This provides the signal
termination at the Receiver inputs. Other options may be used to increase noise tolerance.
8.3.7.2 Receiver Termination Option 2
For additional EMI tolerance, two 50-Ω resistors may be used in place of the single 100-Ω resistor. A small
capacitor is tied from the center point of the 50-Ω resistors to ground (see Figure 31). This provides a high-
frequency low impedance path for noise suppression. Value is not critical, 4.7 nF may be used with general
applications.
8.3.7.3 Receiver Termination Option 3
For high noise environments, an additional voltage divider network may be connected to the center point. This
has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the
range of 100Ω-2KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.8 V. For
example (see Figure 32): V_DD=3.3 V, Rpullup=1 KΩ, Rpulldown=1.2 KΩ; or Rpullup=100 Ω, Rpulldown=120 Ω
(strongest). The smaller values will consume more bias current, but will provide enhanced noise suppression.
8.3.8 Signal Quality Enhancers
The DS90UR124 Deserializer supports two signal quality enhancers. The SLEW pin is used to increase the drive
strength of the LVCMOS outputs when driving heavy loads. SLEW allows output drive strength for high or low
current drive. Default setting is LOW for low drive at 2 mA and HIGH for high drive at 4 mA.
There are two types of Progressive Turnon modes (Fixed and PTO Frequency Spread) to help reduce EMI:
simultaneous switching noise and system ground bounce. The PTOSEL pin introduces bank skew in the
data/clock outputs to limit the number of outputs switching simultaneously. For Fixed-PTO mode, the Deserializer
ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 2 or 1 UI apart in
phase from RCLK for Group 1 and Groups 2, 3, respectively (see Figure 17). In the PTO Frequency Spread
mode, ROUT[23:0] are also grouped into three groups of eight, with each group is separated out of phase with
the adjacent groups (see Figure 18) per every 4 cycles. Note that in the PTO Frequency Spread operating mode
RCLK is also spreading and separated by 1 UI.
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Product Folder Links: DS90UR124-Q1 DS90UR241-Q1