DS90UR124-Q1 Datasheet, PDF (28/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
9.2.2 DS90UR124 Typical Application Connection
3.3V
C1
DS90UR124 (DES)
VDD
VDD
C5
VDD
VDD
C7
3.3V
C3
VDD
VDD
C2
C6
VDD
VDD
C8
C4
C9
Serial
LVDS
R1
Interface
C10
GPO if used, or tie High (ON)
GPOs if used,
or tie Low (OFF)
3.3V
Notes:
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RAOFF = Low (Default)
PTOSEL = Low (Defaut)
SLEW = Low (Default)
RES0 = Low
BISTEN = GPO or Low
BISTM = GPO or Low
RIN+
RIN-
RPWDNB
BISTEN
BISTM
REN
RRFB
RAOFF
PTOSEL
SLEW
RES0(11)
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
RCLK
LOCK
PASS
LVCMOS
Parallel
Interface
C1 to C4 = 0.1 PF
C5 to C8 = 0.01 PF (optional)
C9 to C10 = 100 nF;
50WVDC, NPO or X7R
R1 = 100:
Figure 26. DS90UR124 Connection Diagram
9.2.2.1 Design Requirements
Table 4. DS90UR124 Design Parameters
DESIGN PARAMETER
VDD
DS90UR124-Q1 AC-Coupling Capacitor for RIN±
DS90UR124-Q1 Termination for RIN±
EXAMPLE VALUE
3.3 V
100 nF
100 Ω
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