DS90UR124-Q1 Datasheet, PDF (13/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Parasitic package and
Trace capacitance
DEN ^VCC^/2
(single-ended)
0V
D_OUT±
(differential)
200 mV
DEN ^VCC^/2
(single-ended)
0V
200 mV
D_OUT±
(differential)
DEN
D_OUT+
D_OUT-
5 pF
100:
CLK1
t_TCP
t_TCP
t_LZD
V_CC/2
CLK1
t_ZLD
t_ZHD
DCA
DCA _{DCA DCA}
$OOGDWD³0´V
DCA DCA DCA DCA
t_HZD
V_CC/2
DCA ^{DCA DCA DCA}
$OOGDWD³1´V
DCA DCA DCA DCA
t_TCP
t_TCP
CLK0
CLK0
Figure 8. Serializer Tri-State Test Circuit and Delay
0V
200 mV
0V
200 mV
PWDWN
2.0V
TCLK
D_OUT±
t_PLD
TRI-STATE
t_ZHD or
t_ZLD
Output
Active
0.8V
t_HZD or
t_LZD
TRI-STATE
Figure 9. Serializer PLL Lock Time, and TPWDNB Tri-State Delays
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