DS90UR124-Q1 Datasheet, PDF (26/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
www.ti.com
9.2.1.2.1 Power Considerations
An all LVCMOS design of the Serializer and Deserializer makes them inherently low-power devices. Additionally,
the constant current source nature of the LVDS outputs minimizes the slope of the speed vs. I_DD curve of
LVCMOS designs.
9.2.1.2.2 Noise Margin
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic factors include:
• Serializer: V_DD noise, TCLK jitter (noise bandwidth and out-of-band noise)
• Media: ISI, V_CM noise
• Deserializer: V_DD noise
For a graphical representation of noise margin, see Figure 19.
9.2.1.2.3 Transmission Media
The Serializer and Deserializer are to be used in point-to-point configuration, through a PCB trace, or through
twisted pair cable. In a point-to-point configuration, the transmission media needs be terminated at both ends of
the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100 Ω. Use
cables and connectors that have matched differential impedance to minimize impedance discontinuities. In most
applications that involve cables, the transmission distance will be determined on data rates involved, acceptable
bit error rate and transmission medium.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver Input Tolerance and Differential Threshold
Voltage specifications define the acceptable data eye opening. A differential probe should be used to measure
across the termination resistor at the DS90UR124 inputs. Figure 23 illustrates the eye opening and relationship
to the Receiver Input Tolerance and Differential Threshold Voltage specifications.
Ideal Data Bit
Beginning
Minimum Eye
Width
Ideal Data Bit
End
RxIN_TOL -L
_VTH - VTL
RxIN_TOL -R
t_BIT
(1UI)
Figure 23. Receiver Input Eye Opening
9.2.1.2.4 Live Link Insertion
The Serializer and Deserializer devices support live pluggable applications. The automatic receiver lock to
random data “plug and go” hot insertion capability allows the DS90UR124 to attain lock to the active data stream
during a live insertion event.
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