DS90UR124-Q1 Datasheet, PDF (23/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
8.4 Device Functional Modes
TPWDNB
(Pin 9)
L
H
H
H
H
DEN
(Pin 18)
X
L
H
H
H
Table 1. DS90UR241 Serializer Truth Table
RAOFF
(Pin 12)
X
X
X
L
H
Tx PLL Status
(Internal)
X
X
Not Locked
Locked
Locked
LVDS Outputs
(Pins 19 and 20)
Hi-Z
Hi-Z
Hi-Z
Serialized Data with Embedded Clock
(DS90UR124 compatible)
Serialized Data with Embedded Clock
(DS90C124 compatible)
RPWDNB
(Pin 48)
L
H
H
H
H
REN
(Pin 60)
X
L
H
H
H
Table 2. DS90UR124 Deserializer Truth Table
RAOFF
(Pin 63)
X
X
Rx PLL Status
(Internal)
X
X
ROUTn and RCLK
(See Pin Diagram)
Hi Z
Hi Z
X
Not Locked
Hi Z
L
Locked
Data and RCLK Active
(DS90UR241 compatible)
H
Locked
Data and RCLK Active
(DS90C241 compatible)
LOCK
(Pin 23)
Hi Z
L = PLL Unocked;
H = PLL Locked
L
H
H
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