DS90UR124-Q1 Datasheet, PDF (12/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 4. Deserializer Output Checkerboard Pattern
D_OUT+
10 pF
100:
Vdiff
80%
20%
80%
Vdiff = 0V
20%
D_OUT-
10 pF
Vdiff = (D_OUT+) - (D_OUT-)
t_LLHT
t_LHLT
Figure 5. Serializer LVDS Output Load and Transition Times
TCLK
80%
20%
80%
V_DD
20%
0V
t_CLKT
t_CLKT
Figure 6. Serializer Input Clock Transition Times
t_TCP
TCLK
V_DD/2
V_DD/2
V_DD/2
t_DIS
t_DIH
DIN [0:23] _VDD/2
Setup
Hold
V_DD/2
V_DD
0V
Figure 7. Serializer Setup and Hold Times
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