DS90UR124-Q1 Datasheet, PDF (29/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
9.2.2.2 Detailed Design Procedure
Figure 26 shows a typical application of the DS90UR124 deserializer for an 33-MHz 18-bit Color Display
Application. The RIN± inputs must have an external series 0.1-μF AC-coupling capacitor and 100-Ω parallel
termination on the high-speed serial lines. The deserializer does not have an internal termination. Bypass
capacitors are placed near the power supply pins. At a minimum, four 0.1-μF capacitors should be used for local
device bypassing. Ferrite beads may be needed on the VDDs for effective noise suppression. Additional
capacitors may be needed as the number and values of the capacitors will depend on meeting the power noise
specification of the part. The interface to the display is with 3.3-V LVCMOS levels. An RC delay is placed on the
PDB signal to delay the enabling of the device until power is stable.
9.2.2.3 Application Curves
43 MHz RX
Pixel Clock
Output
(1 V/DIV)
1.2 Gbps TX
Serial Data
Output
(200 mV/DIV)
Time (10 ns/DIV)
Figure 27. DS90UR241 Serial Stream and DS90UR124
43-MHz PCLK Output
Time (5 ns/DIV)
Figure 28. DS90UR124 PCLK Output at 43 MHz (Enlarged)
10 Power Supply Recommendations
This device is designed to operate from an input core voltage supply of 3.3 V. Some devices provide separate
power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between
different sections of the circuit. Separate planes on the PCB are typically. Pin description tables typically provide
guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may
be used to provide clean power to sensitive circuits such as PLLs.
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