DS90UR124-Q1 Datasheet, PDF (14/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
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D_IN
SYMBOL N
TCLK
SYMBOL N+1
SYMBOL N+2
t_SD
SYMBOL N+3
D_OUT0-23
DCA, DCB
STOP START
STOP START
STOP START
STOP START
STOP
SYMBOL N-4 ^{BIT BIT} SYMBOL N-3 ^{BIT BIT} SYMBOL N-2 ^{BIT BIT} SYMBOL N-1 ^{BIT BIT} SYMBOL N ^BIT
012
23
012
23
012
23
012
23
012
23
Figure 10. Serializer Delay
Ideal Data Bit
Beginning
Ideal Data Bit
End
TxOUT_E_O
t_BIT(1/2 UI)
t_BIT(1/2 UI)
Ideal Center Position (t_BIT/2)
t_BIT (1 UI)
Figure 11. Transmitter Output Eye Opening (TxOUT_E_O)
24
D_IN
D_OUT+
R_L
20194528 _DOUT-
TCLK
VOD = (D_OUT+) – (D_OUT−)
Differential output signal is shown as (D_OUT+) – (D_OUT−), device in Data Transfer mode.
Figure 12. Serializer V_OD Diagram
Deserializer
4 pF
lumped
80%
20%
80%
20%
t_CLH
t_CHL
Figure 13. Deserializer LVCMOS Output Load and Transition Times
14
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