DS90UR124-Q1 Datasheet, PDF (3/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
5 Description (continued)
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal
DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random
lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
6 Pin Configuration and Functions
PFB Package
48-Pin TQFP
Top View
D_IN[10]
37
D_IN[11]
38
D_IN[12]
39
D_IN[13]
40
D_IN[14]
41
V_DD
42
V_SS
43
D_IN[15]
44
D_IN[16]
45
D_IN[17]
46
D_IN[18]
47
D_IN[19]
48
DS90UR241
24
VODSEL
23
PRE
22
V_DD
21
V_SS
20
D_OUT+
19
D_OUT-
18
DEN
17
V_SS
16
V_DD
15
V_SS
14
V_DD
13
RES0
Pin Functions: PFB Package
PIN
I/O
NO.
NAME
DESCRIPTION
LVCMOS PARALLEL INTERFACE PINS
4-1,
48-44,
41-32,
29-25
D_IN[23:0]
LVCMOS_I Transmitter Parallel Interface Data Input Pins. Tie LOW if unused; do not float.
10
TCLK
LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
CONTROL AND CONFIGURATION PINS
Transmitter Data Enable
18
DEN
LVCMOS_I
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver D_OUT (+/-) Outputs
are in Tri-state, PLL still operational and locked to TCLK.
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
23
PRE
LVCMOS_I Pre-emphasis is active when input is tied to VSS through external resistor R_PRE. Resistor value
determines pre-emphasis level. Recommended value R_PRE ≥ 6 kΩ; I_max = [48 / R_PRE], R_PREmin =
6 kΩ
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