DS90UR124-Q1 Datasheet, PDF (18/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
8 Detailed Description
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8.1 Overview
The DS90UR241 Serializer and DS90UR124 Deserializer chipset is an easy-to-use transmitter and receiver pair
that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 1.03 Gbps
throughput. The DS90UR241 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS
serial data stream with embedded clock and scrambles / DC Balances the data to enhance signal quality to
support AC coupling. The DS90UR124 receives the LVDS serial data stream and converts it back into a 24-bit
wide parallel data and recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data up
to 10 meters over shielded twisted pair (STP) at clock speeds from 5 MHz to 43 MHz.
The Deserializer can attain lock to a data stream without the use of a separate reference clock source, greatly
simplifying system complexity and overall cost. The Deserializer synchronizes to the Serializer regardless of data
pattern, delivering true automatic “plug and lock” performance. It will lock to the incoming serial stream without
the need of special training patterns or sync characters. The Deserializer recovers the clock and data by
extracting the embedded clock information and validating data integrity from the incoming data stream and then
deserializes the data. The Deserializer monitors the incoming clock information, determines lock status, and
asserts the LOCK output high when lock occurs.
In addition, the Deserializer also supports an optional @SPEED BIST (Built In Self Test) mode, BIST error flag,
and LOCK status reporting pin. Signal quality on the wide parallel output is controlled by the SLEW control and
bank slew (PTOSEL) inputs to help reduce noise and system EMI. Each device has a power down control to
enable efficient operation in various applications.
8.2 Functional Block Diagram
VODSEL
PRE
DEN
RAOFF
REN
24
D_IN
TRFB
D_OUT+
D_OUT-
R_IN+
R_IN-
24
R_OUT
TCLK
PLL
TPWDNB
Timing
and
Control
SERIALIZER ± DS90UR241
RAOFF
RRFB
RPWDNB
BISTEN
BISTM
SLEW
PTOSEL
PLL
Timing
and
Control
LOCK
Clock
Recovery
DESERIALIZER ± DS90UR124
RCLK
PASS
8.3 Feature Description
8.3.1 Initialization and Locking Mechanism
Initialization of the DS90UR241 and DS90UR124 must be established before each device sends or receives
data. Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers
locks to the input clock source, the Deserializer synchronizes to the Serializers as the second and final
initialization step.
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