DS90UR124-Q1 Datasheet, PDF (20/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
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Feature Description (continued)
8.3.3 Resynchronization
If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock
edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer
then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock
edge, identifies it, and then proceeds through the locking process.
The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid.
The system may monitor the LOCK pin to determine whether data on the ROUT is valid.
8.3.4 Powerdown
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power
when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into powerdown
mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is
driven low. In powerdown, the PLL stops and the outputs go into Tri-state, disabling load current and reducing
current supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL
must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization
before data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In
powerdown mode, the PLL stops and the outputs enter Tri-state. To bring the Deserializer block out of the
powerdown state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer
will initialize and assert LOCK high when it is locked to the embedded clock.
8.3.5 Tri-State
For the Serializer, Tri-state is entered when the DEN or TPWDNB pin is driven low. This will Tri-state both driver
output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state as
long as all other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deserializer enters Tri-state. Consequently, the receiver
output pins (ROUT0–ROUT23) and RCLK will enter Tri-state. The LOCK output remains active, reflecting the
state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and
power-off (V_DD = 0 V).
8.3.6 Pre-Emphasis
The DS90UR241 features a Pre-Emphasis function used to compensate for long or lossy transmission media.
Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current
during transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media. Pre-Emphasis adds extra current during LVDS logic transition to reduce
the cable loading effects and increase driving distance. In addition, Pre-Emphasis helps provide faster
transitions, increased eye openings, and improved signal integrity. The ability of the DS90UR241 to use the Pre-
Emphasis feature will extend the transmission distance up to 10 meters in most cases.
To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to Vss in order to set
the additional current level. Values of Rpre should be between 6 kΩ and 100 MΩ. Values less than 6 kΩ should
not be used. A lower input resistor value on the ”PRE” pin increases the magnitude of dynamic current during
data transition. The additional source current is based on the following formula: PRE = (R_PRE ≥ 6 kΩ); I_MAX = [48 /
R_PRE]. For example if Rpre = 15 kΩ , then the Pre-Emphasis current is increase by an additional 3.2 mA.
The amount of Pre-Emphasis for a given media will depend on the transmission distance of the application. In
general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This can result in
excessive noise, crosstalk and increased power dissipation. For short cables or distances, Pre-Emphasis may
not be required. Signal quality measurements are recommended to determine the proper amount of Pre-
Emphasis for each application.
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