DS90UR124-Q1 Datasheet, PDF (31/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

www.ti.com
DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Layout Guidelines (continued)
Additional general guidance can be found in the LVDS Owner’s Manual (SNLA187) - available in PDF format
from the TI web site at: www.ti.com/lvds
D_OUT+ 100 nF
100 nF R_IN+
100:
100:
D_OUT-
100 nF
100 nF ^RIN^-
Figure 29. AC-Coupled Application
1 CLK cycle
*Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC
Balanced
Figure 30. Single Serialized LVDS Bitstream*
DS90UR241
DS90UR241
0.1 PF
100:
0.1 PF
0.1 PF
50:
4.7 nF
50:
0.1 PF
RIN+
DS90UR124
RIN-
Figure 31. Receiver Termination Option 2
0.1 PF
100:
VDD
0.1 PF
R_PU
50:
R_PD
4.7 nF
50:
0.1 PF
0.1 PF
RIN+
DS90UR124
RIN-
Figure 32. Receiver Termination Option 3
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: DS90UR124-Q1 DS90UR241-Q1