DS90UR124-Q1 Datasheet, PDF (17/41 Pages) Texas Instruments – 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
R_OUT
(Ideal)
½ Symbol ½ Symbol
RCLK
R_OUT
GRP1
1 + 3/28 Symbol
1 - 2/28 Symbol
1 + 3/28 Symbol
1 - 4/28 Symbol
2 UI EARLY
1 UI LATE
1 UI EARLY
2 UI LATE
Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI).
Group 2 will be latched internally by sequence of (late 1UI, early 1UI, late 2UI, early 2UI).
Group 3 will be latched internally by sequence of (early 1UI, late 2UI, early 2UI, late 1UI).
2 UI EARLY
Figure 18. Deserializer Setup and Hold Times and PTO Spread, PTOSEL = L
Ideal Data Bit
Beginning
Sampling
Window
Ideal Data Bit
End
RxIN_TOL -L
RxIN_TOL -R
Ideal Center Position (t_BIT/2)
t_BIT (1 UI)
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
Figure 19. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
7.9 Typical Characteristics
Time (2.5 ns/DIV)
Figure 20. DS90UR241 DOUT± With PCLK at 43 MHz
Measured at RIN± Termination
Time (5 ns/DIV)
Figure 21. DS90UR124 PCLK Output at 43 MHz
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