SM470R1B1M-HT Datasheet, PDF (56/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
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SDA
SCL
t_w(SDAH)
t_w(SCLL)
t_r(SCL)
t_{su(SDA−SCLH)}
t_w(SCLH)
t_w(SP)
t_{su(SCLH−SDAH)}
t_c(SCL)
t_{h(SCLL−SDAL)}
t_f(SCL)
t_{h(SDA−SCLL)}
t_{h(SCLL−SDAL})
t_{su(SCLH−SDAL)}
Stop Start
Repeated
Stop
D. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
E. The maximum t_h(SDA-SCLL) needs only be met if the device does not stretch the LOW period (t_w(SCLL)) of the SCL
signal.
F. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement t_su(SDA-SCLH) ≥ 250
ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t_r max + t_su(SDA-SCLH).
G. C_b = total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
Figure 21. I2C Timings
STANDARD CAN CONTROLLER (SCC) MODE TIMINGS
Dynamic Characteristics for the CANSTX and CANSRX Pins⁽¹⁾
t_d(CANSTX)
t_d(CANSRX)
PARAMETER
Delay time, transmit shift register to CANSTX pin⁽²⁾
Delay time, CANSRX pin to receive shift register
(1) Not production tested.
(2) These values do not include the rise/fall times of the output buffer.
MIN
MAX UNIT
15 ns
5 ns
56
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