SM470R1B1M-HT Datasheet, PDF (17/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
www.ti.com
TERMINAL
NAME
RST
AWD
TCK
TDI
TDO
TEST
TMS
TMS2
TRST
FLTP2
V_CCP
V_CC
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
Table 4. Terminal Functions (continued)
PAD
NO.
124
39
79
77
78
127
18
17
151
135
134
14
34
56
95
126
133
HFQ/
HKP
PIN
NO. ⁽⁴⁾
TYPE ^{(1) (2)}
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN ⁽³⁾
69
3.3 V
4 mA
IPU (20 µA)
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
21
3.3 V
8 mA
TEST/DEBUG (T/D)
45
IPD (20 µA)
43
3.3 V
8 mA
IPU (20 µA)
44
8 mA
IPD (20 µA)
72
IPD (20 µA)
11
8 mA
IPU (20 µA)
10
3.3 V
8 mA
IPU (20 µA)
84
IPD (20 µA)
FLASH
77
NC
NC
76
3.3-V PWR
SUPPLY VOLTAGE CORE (1.8 V)
8
17
28
1.8-V PWR
54
71
75
DESCRIPTION
Bidirectional reset. The internal circuitry can
assert a reset, and an external system reset
can assert a device reset.
On this pin, the output buffer is implemented
as an open drain (drives low only).
To ensure an external reset is not arbitrarily
generated, TI recommends that an external
pullup resistor be connected to this pin.
Analog watchdog reset. The AWD pin
provides a system reset if the WD KEY is
not written in time by the system, providing
an external RC network circuit is connected.
If the user is not using AWD, TI
recommends that this pin be connected to
ground or pulled down to ground by an
external resistor.
For more details on the external RC network
circuit, see the TMS470R1x System Module
Reference Guide (literature number
SPNU189).
Test clock. TCK controls the test hardware
(JTAG).
Test data in. TDI inputs serial data to the
test instruction register, test data register,
and programmable test address (JTAG).
Test data out. TDO outputs serial data from
the test instruction register, test data
register, identification register, and
programmable test address (JTAG).
Test enable. Reserved for internal use only.
TI recommends that this pin be connected to
ground or pulled down to ground by an
external resistor.
Serial input for controlling the state of the
CPU test access port (TAP) controller
(JTAG).
Serial input for controlling the second TAP.
TI recommends that this pin be connected to
V_CCIO or pulled up to V_CCIO by an external
resistor.
Test hardware reset to TAP1 and TAP2.
IEEE Standard 1149-1 (JTAG) Boundary-
Scan Logic. TI recommends that this pin be
pulled down to ground by an external
resistor.
Flash test pad 2. For proper operation,
this pin must not be connected [no
connect (NC)].
Flash external pump voltage (3.3 V)
Core logic supply voltage
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
17